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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
181 lines
6.6 KiB
Diff
181 lines
6.6 KiB
Diff
From 244012f3f879d4709be68e7ddabc064268bbd69e Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Thu, 28 Dec 2023 00:38:08 +0800
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Subject: [PATCH 27/50] net: ethernet: qualcomm: Add PPE L2 bridge
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initialization
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The per-port L2 bridge settings are initialized as follows:
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For PPE CPU port, the PPE bridge Tx is enabled and FDB learn is
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disabled. For PPE physical port, the PPE bridge Tx is disabled
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and FDB learn is enabled by default and the L2 forward action
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is initialized as forward to CPU port.
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Change-Id: Ida42464f1d5e53583a434a11b19e6501c649d44e
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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---
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.../net/ethernet/qualcomm/ppe/ppe_config.c | 68 ++++++++++++++++++-
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drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 54 +++++++++++++++
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2 files changed, 121 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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@@ -1957,6 +1957,68 @@ static int ppe_queues_to_ring_init(struc
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return ppe_ring_queue_map_set(ppe_dev, 0, queue_bmap);
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}
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+/* Initialize PPE bridge configuration. */
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+static int ppe_bridge_init(struct ppe_device *ppe_dev)
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+{
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+ u32 reg, mask, port_cfg[4], vsi_cfg[2];
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+ int ret, i;
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+
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+ /* CPU port0 enable bridge Tx and disable FDB new address
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+ * learning and station move address learning.
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+ */
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+ mask = PPE_PORT_BRIDGE_TXMAC_EN;
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+ mask |= PPE_PORT_BRIDGE_NEW_LRN_EN;
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+ mask |= PPE_PORT_BRIDGE_STA_MOVE_LRN_EN;
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+ ret = regmap_update_bits(ppe_dev->regmap,
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+ PPE_PORT_BRIDGE_CTRL_ADDR,
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+ mask,
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+ PPE_PORT_BRIDGE_TXMAC_EN);
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+ if (ret)
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+ return ret;
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+
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+ for (i = 1; i < ppe_dev->num_ports; i++) {
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+ /* Set Invalid VSI forwarding to CPU port0 if no VSI
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+ * is assigned to the port.
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+ */
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+ reg = PPE_L2_VP_PORT_TBL_ADDR + PPE_L2_VP_PORT_TBL_INC * i;
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+ ret = regmap_bulk_read(ppe_dev->regmap, reg,
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+ port_cfg, ARRAY_SIZE(port_cfg));
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+
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+ if (ret)
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+ return ret;
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+
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+ PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(port_cfg, true);
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+ PPE_L2_PORT_SET_DST_INFO(port_cfg, 0);
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+
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+ ret = regmap_bulk_write(ppe_dev->regmap, reg,
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+ port_cfg, ARRAY_SIZE(port_cfg));
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+ if (ret)
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+ return ret;
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+ }
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+
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+ for (i = 0; i < PPE_VSI_TBL_NUM; i++) {
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+ /* Enable VSI bridge forward address learning and set VSI
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+ * forward member includes CPU port0.
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+ */
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+ PPE_VSI_SET_MEMBER_PORT_BITMAP(vsi_cfg, BIT(0));
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+ PPE_VSI_SET_UUC_BITMAP(vsi_cfg, BIT(0));
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+ PPE_VSI_SET_UMC_BITMAP(vsi_cfg, BIT(0));
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+ PPE_VSI_SET_BC_BITMAP(vsi_cfg, BIT(0));
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+ PPE_VSI_SET_NEW_ADDR_LRN_EN(vsi_cfg, true);
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+ PPE_VSI_SET_NEW_ADDR_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD);
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+ PPE_VSI_SET_STATION_MOVE_LRN_EN(vsi_cfg, true);
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+ PPE_VSI_SET_STATION_MOVE_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD);
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+
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+ reg = PPE_VSI_TBL_ADDR + PPE_VSI_TBL_INC * i;
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+ ret = regmap_bulk_write(ppe_dev->regmap, reg,
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+ vsi_cfg, ARRAY_SIZE(vsi_cfg));
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+ if (ret)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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/* Initialize PPE device to handle traffic correctly. */
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static int ppe_dev_hw_init(struct ppe_device *ppe_dev)
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{
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@@ -1978,7 +2040,11 @@ static int ppe_dev_hw_init(struct ppe_de
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if (ret)
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return ret;
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- return ppe_queues_to_ring_init(ppe_dev);
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+ ret = ppe_queues_to_ring_init(ppe_dev);
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+ if (ret)
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+ return ret;
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+
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+ return ppe_bridge_init(ppe_dev);
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}
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int ppe_hw_config(struct ppe_device *ppe_dev)
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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@@ -126,6 +126,18 @@
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#define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \
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u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_TX_CNT_EN)
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+/* PPE port bridge configuration */
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+#define PPE_PORT_BRIDGE_CTRL_ADDR 0x60300
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+#define PPE_PORT_BRIDGE_CTRL_NUM 8
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+#define PPE_PORT_BRIDGE_CTRL_INC 4
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+#define PPE_PORT_BRIDGE_NEW_LRN_EN BIT(0)
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+#define PPE_PORT_BRIDGE_NEW_FWD_CMD GENMASK(2, 1)
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+#define PPE_PORT_BRIDGE_STA_MOVE_LRN_EN BIT(3)
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+#define PPE_PORT_BRIDGE_STA_MOVE_FWD_CMD GENMASK(5, 4)
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+#define PPE_PORT_BRIDGE_ISOLATION_BITMAP GENMASK(15, 8)
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+#define PPE_PORT_BRIDGE_TXMAC_EN BIT(16)
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+#define PPE_PORT_BRIDGE_PROMISC_EN BIT(17)
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+
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#define PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00
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#define PPE_MC_MTU_CTRL_TBL_NUM 8
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#define PPE_MC_MTU_CTRL_TBL_INC 4
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@@ -133,6 +145,36 @@
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#define PPE_MC_MTU_CTRL_TBL_MTU_CMD GENMASK(15, 14)
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#define PPE_MC_MTU_CTRL_TBL_TX_CNT_EN BIT(16)
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+/* PPE VSI configurations */
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+#define PPE_VSI_TBL_ADDR 0x63800
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+#define PPE_VSI_TBL_NUM 64
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+#define PPE_VSI_TBL_INC 0x10
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+#define PPE_VSI_W0_MEMBER_PORT_BITMAP GENMASK(7, 0)
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+#define PPE_VSI_W0_UUC_BITMAP GENMASK(15, 8)
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+#define PPE_VSI_W0_UMC_BITMAP GENMASK(23, 16)
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+#define PPE_VSI_W0_BC_BITMAP GENMASK(31, 24)
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+#define PPE_VSI_W1_NEW_ADDR_LRN_EN BIT(0)
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+#define PPE_VSI_W1_NEW_ADDR_FWD_CMD GENMASK(2, 1)
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+#define PPE_VSI_W1_STATION_MOVE_LRN_EN BIT(3)
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+#define PPE_VSI_W1_STATION_MOVE_FWD_CMD GENMASK(5, 4)
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+
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+#define PPE_VSI_SET_MEMBER_PORT_BITMAP(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_MEMBER_PORT_BITMAP)
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+#define PPE_VSI_SET_UUC_BITMAP(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_UUC_BITMAP)
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+#define PPE_VSI_SET_UMC_BITMAP(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_UMC_BITMAP)
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+#define PPE_VSI_SET_BC_BITMAP(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_BC_BITMAP)
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+#define PPE_VSI_SET_NEW_ADDR_LRN_EN(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_NEW_ADDR_LRN_EN)
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+#define PPE_VSI_SET_NEW_ADDR_FWD_CMD(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_NEW_ADDR_FWD_CMD)
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+#define PPE_VSI_SET_STATION_MOVE_LRN_EN(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_STATION_MOVE_LRN_EN)
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+#define PPE_VSI_SET_STATION_MOVE_FWD_CMD(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_STATION_MOVE_FWD_CMD)
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+
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/* PPE port control configuration, the MTU and MRU configs. */
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#define PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000
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#define PPE_MRU_MTU_CTRL_TBL_NUM 256
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@@ -170,6 +212,18 @@
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#define PPE_IN_L2_SERVICE_TBL_RX_CNT_EN BIT(30)
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#define PPE_IN_L2_SERVICE_TBL_TX_CNT_EN BIT(31)
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+/* L2 Port configurations */
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+#define PPE_L2_VP_PORT_TBL_ADDR 0x98000
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+#define PPE_L2_VP_PORT_TBL_NUM 256
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+#define PPE_L2_VP_PORT_TBL_INC 0x10
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+#define PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN BIT(0)
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+#define PPE_L2_VP_PORT_W0_DST_INFO GENMASK(9, 2)
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+
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+#define PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN)
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+#define PPE_L2_PORT_SET_DST_INFO(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_L2_VP_PORT_W0_DST_INFO)
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+
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#define PPE_TL_SERVICE_TBL_ADDR 0x306000
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#define PPE_TL_SERVICE_TBL_NUM 256
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#define PPE_TL_SERVICE_TBL_INC 4
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