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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
316 lines
11 KiB
Diff
316 lines
11 KiB
Diff
From 12a50075552d0e2ada65c039e5a09ca50421f152 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Tue, 26 Dec 2023 19:34:49 +0800
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Subject: [PATCH 20/50] net: ethernet: qualcomm: Add PPE queue management
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config
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QM (queue management) config decides the length of PPE port queues
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and the threshold to drop packet.
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There are two types of PPE queue, unicast queue (0-255) and multicast
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queue (256-299) are configured with different length, which are used
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to forward the different types of traffic.
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Change-Id: I74ffcb6a39618ca8f585b5204d483fb45edecba8
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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.../net/ethernet/qualcomm/ppe/ppe_config.c | 176 +++++++++++++++++-
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drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 82 ++++++++
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2 files changed, 257 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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@@ -43,6 +43,27 @@ struct ppe_bm_port_config {
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bool dynamic;
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};
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+/**
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+ * struct ppe_qm_queue_config - PPE queue config.
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+ * @queue_start: PPE start of queue ID.
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+ * @queue_end: PPE end of queue ID.
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+ * @prealloc_buf: Queue dedicated buffer number.
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+ * @ceil: Ceil to start drop packet from queue.
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+ * @weight: Weight value.
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+ * @resume_offset: Resume offset from the threshold.
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+ * @dynamic: Threshold value is decided dynamically or statically.
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+ *
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+ */
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+struct ppe_qm_queue_config {
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+ unsigned int queue_start;
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+ unsigned int queue_end;
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+ unsigned int prealloc_buf;
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+ unsigned int ceil;
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+ unsigned int weight;
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+ unsigned int resume_offset;
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+ bool dynamic;
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+};
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+
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static int ipq9574_ppe_bm_group_config = 1550;
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static struct ppe_bm_port_config ipq9574_ppe_bm_port_config[] = {
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{
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@@ -91,6 +112,31 @@ static struct ppe_bm_port_config ipq9574
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},
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};
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+/* Default QM group settings for IPQ9754. */
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+static int ipq9574_ppe_qm_group_config = 2000;
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+
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+/* Default QM settings for unicast and multicast queues for IPQ9754. */
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+static struct ppe_qm_queue_config ipq9574_ppe_qm_queue_config[] = {
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+ {
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+ .queue_start = 0,
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+ .queue_end = 255,
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+ .prealloc_buf = 0,
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+ .ceil = 400,
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+ .weight = 4,
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+ .resume_offset = 36,
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+ .dynamic = true,
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+ },
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+ {
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+ .queue_start = 256,
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+ .queue_end = 299,
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+ .prealloc_buf = 0,
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+ .ceil = 250,
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+ .weight = 0,
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+ .resume_offset = 36,
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+ .dynamic = false,
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+ },
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+};
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+
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static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id,
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struct ppe_bm_port_config port_cfg)
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{
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@@ -175,7 +221,135 @@ bm_config_fail:
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return ret;
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}
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+/* Configure PPE hardware queue depth, which is decided by the threshold
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+ * of queue.
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+ */
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+static int ppe_config_qm(struct ppe_device *ppe_dev)
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+{
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+ struct ppe_qm_queue_config *queue_cfg;
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+ int ret, i, queue_id, queue_cfg_count;
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+ u32 reg, multicast_queue_cfg[5];
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+ u32 unicast_queue_cfg[4];
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+ u32 group_cfg[3];
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+
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+ /* Assign the buffer number to the group 0 by default. */
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+ reg = PPE_AC_GRP_CFG_TBL_ADDR;
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+ ret = regmap_bulk_read(ppe_dev->regmap, reg,
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+ group_cfg, ARRAY_SIZE(group_cfg));
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+ if (ret)
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+ goto qm_config_fail;
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+
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+ PPE_AC_GRP_SET_BUF_LIMIT(group_cfg, ipq9574_ppe_qm_group_config);
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+
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+ ret = regmap_bulk_write(ppe_dev->regmap, reg,
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+ group_cfg, ARRAY_SIZE(group_cfg));
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+ if (ret)
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+ goto qm_config_fail;
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+
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+ queue_cfg = ipq9574_ppe_qm_queue_config;
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+ queue_cfg_count = ARRAY_SIZE(ipq9574_ppe_qm_queue_config);
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+ for (i = 0; i < queue_cfg_count; i++) {
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+ queue_id = queue_cfg[i].queue_start;
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+
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+ /* Configure threshold for dropping packet from unicast queue
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+ * and multicast queue, which belong to the different queue ID.
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+ */
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+ while (queue_id <= queue_cfg[i].queue_end) {
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+ if (queue_id < PPE_AC_UNI_QUEUE_CFG_TBL_NUM) {
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+ reg = PPE_AC_UNI_QUEUE_CFG_TBL_ADDR +
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+ PPE_AC_UNI_QUEUE_CFG_TBL_INC * queue_id;
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+
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+ ret = regmap_bulk_read(ppe_dev->regmap, reg,
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+ unicast_queue_cfg,
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+ ARRAY_SIZE(unicast_queue_cfg));
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+ if (ret)
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+ goto qm_config_fail;
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+
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+ PPE_AC_UNI_QUEUE_SET_EN(unicast_queue_cfg, true);
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+ PPE_AC_UNI_QUEUE_SET_GRP_ID(unicast_queue_cfg, 0);
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+ PPE_AC_UNI_QUEUE_SET_PRE_LIMIT(unicast_queue_cfg,
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+ queue_cfg[i].prealloc_buf);
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+ PPE_AC_UNI_QUEUE_SET_DYNAMIC(unicast_queue_cfg,
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+ queue_cfg[i].dynamic);
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+ PPE_AC_UNI_QUEUE_SET_WEIGHT(unicast_queue_cfg,
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+ queue_cfg[i].weight);
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+ PPE_AC_UNI_QUEUE_SET_THRESHOLD(unicast_queue_cfg,
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+ queue_cfg[i].ceil);
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+ PPE_AC_UNI_QUEUE_SET_GRN_RESUME(unicast_queue_cfg,
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+ queue_cfg[i].resume_offset);
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+
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+ ret = regmap_bulk_write(ppe_dev->regmap, reg,
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+ unicast_queue_cfg,
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+ ARRAY_SIZE(unicast_queue_cfg));
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+ if (ret)
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+ goto qm_config_fail;
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+ } else {
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+ reg = PPE_AC_MUL_QUEUE_CFG_TBL_ADDR +
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+ PPE_AC_MUL_QUEUE_CFG_TBL_INC * queue_id;
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+
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+ ret = regmap_bulk_read(ppe_dev->regmap, reg,
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+ multicast_queue_cfg,
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+ ARRAY_SIZE(multicast_queue_cfg));
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+ if (ret)
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+ goto qm_config_fail;
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+
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+ PPE_AC_MUL_QUEUE_SET_EN(multicast_queue_cfg, true);
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+ PPE_AC_MUL_QUEUE_SET_GRN_GRP_ID(multicast_queue_cfg, 0);
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+ PPE_AC_MUL_QUEUE_SET_GRN_PRE_LIMIT(multicast_queue_cfg,
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+ queue_cfg[i].prealloc_buf);
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+ PPE_AC_MUL_QUEUE_SET_GRN_THRESHOLD(multicast_queue_cfg,
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+ queue_cfg[i].ceil);
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+ PPE_AC_MUL_QUEUE_SET_GRN_RESUME(multicast_queue_cfg,
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+ queue_cfg[i].resume_offset);
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+
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+ ret = regmap_bulk_write(ppe_dev->regmap, reg,
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+ multicast_queue_cfg,
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+ ARRAY_SIZE(multicast_queue_cfg));
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+ if (ret)
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+ goto qm_config_fail;
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+ }
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+
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+ /* Enable enqueue */
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+ reg = PPE_ENQ_OPR_TBL_ADDR + PPE_ENQ_OPR_TBL_INC * queue_id;
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+ ret = regmap_update_bits(ppe_dev->regmap, reg,
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+ PPE_ENQ_OPR_TBL_ENQ_DISABLE,
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+ FIELD_PREP(PPE_ENQ_OPR_TBL_ENQ_DISABLE, false));
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+ if (ret)
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+ goto qm_config_fail;
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+
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+ /* Enable dequeue */
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+ reg = PPE_DEQ_OPR_TBL_ADDR + PPE_DEQ_OPR_TBL_INC * queue_id;
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+ ret = regmap_update_bits(ppe_dev->regmap, reg,
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+ PPE_DEQ_OPR_TBL_DEQ_DISABLE,
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+ FIELD_PREP(PPE_ENQ_OPR_TBL_ENQ_DISABLE, false));
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+ if (ret)
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+ goto qm_config_fail;
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+
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+ queue_id++;
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+ }
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+ }
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+
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+ /* Enable queue counter for all PPE hardware queues. */
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+ ret = regmap_update_bits(ppe_dev->regmap, PPE_EG_BRIDGE_CONFIG_ADDR,
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+ PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN,
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+ PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN);
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+ if (ret)
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+ goto qm_config_fail;
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+
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+ return 0;
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+
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+qm_config_fail:
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+ dev_err(ppe_dev->dev, "PPE QM config error %d\n", ret);
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+ return ret;
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+}
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+
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int ppe_hw_config(struct ppe_device *ppe_dev)
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{
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- return ppe_config_bm(ppe_dev);
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+ int ret;
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+
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+ ret = ppe_config_bm(ppe_dev);
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+ if (ret)
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+ return ret;
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+
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+ return ppe_config_qm(ppe_dev);
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}
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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@@ -11,6 +11,14 @@
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* BM port (0-7) is matched to EDMA port 0, BM port (8-13) is matched
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* to PPE physical port 1-6, BM port 14 is matched to EIP.
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*/
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+#define PPE_EG_BRIDGE_CONFIG_ADDR 0x20044
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+#define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN BIT(2)
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+
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+#define PPE_DEQ_OPR_TBL_ADDR 0x430000
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+#define PPE_DEQ_OPR_TBL_NUM 300
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+#define PPE_DEQ_OPR_TBL_INC 0x10
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+#define PPE_DEQ_OPR_TBL_DEQ_DISABLE BIT(0)
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+
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#define PPE_BM_PORT_FC_MODE_ADDR 0x600100
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#define PPE_BM_PORT_FC_MODE_INC 0x4
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#define PPE_BM_PORT_FC_MODE_EN BIT(0)
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@@ -51,4 +59,78 @@
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#define PPE_BM_PORT_FC_SET_PRE_ALLOC(tbl_cfg, value) \
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u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_PRE_ALLOC)
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+/* PPE unicast queue (0-255) configurations. */
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+#define PPE_AC_UNI_QUEUE_CFG_TBL_ADDR 0x848000
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+#define PPE_AC_UNI_QUEUE_CFG_TBL_NUM 256
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+#define PPE_AC_UNI_QUEUE_CFG_TBL_INC 0x10
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+#define PPE_AC_UNI_QUEUE_CFG_W0_EN BIT(0)
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+#define PPE_AC_UNI_QUEUE_CFG_W0_WRED_EN BIT(1)
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+#define PPE_AC_UNI_QUEUE_CFG_W0_FC_EN BIT(2)
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+#define PPE_AC_UNI_QUEUE_CFG_W0_COLOR_AWARE BIT(3)
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+#define PPE_AC_UNI_QUEUE_CFG_W0_GRP_ID GENMASK(5, 4)
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+#define PPE_AC_UNI_QUEUE_CFG_W0_PRE_LIMIT GENMASK(16, 6)
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+#define PPE_AC_UNI_QUEUE_CFG_W0_DYNAMIC BIT(17)
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+#define PPE_AC_UNI_QUEUE_CFG_W0_WEIGHT GENMASK(20, 18)
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+#define PPE_AC_UNI_QUEUE_CFG_W0_THRESHOLD GENMASK(31, 21)
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+#define PPE_AC_UNI_QUEUE_CFG_W3_GRN_RESUME GENMASK(23, 13)
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+
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+#define PPE_AC_UNI_QUEUE_SET_EN(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNI_QUEUE_CFG_W0_EN)
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+#define PPE_AC_UNI_QUEUE_SET_GRP_ID(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNI_QUEUE_CFG_W0_GRP_ID)
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+#define PPE_AC_UNI_QUEUE_SET_PRE_LIMIT(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNI_QUEUE_CFG_W0_PRE_LIMIT)
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+#define PPE_AC_UNI_QUEUE_SET_DYNAMIC(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNI_QUEUE_CFG_W0_DYNAMIC)
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+#define PPE_AC_UNI_QUEUE_SET_WEIGHT(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNI_QUEUE_CFG_W0_WEIGHT)
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+#define PPE_AC_UNI_QUEUE_SET_THRESHOLD(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_UNI_QUEUE_CFG_W0_THRESHOLD)
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+#define PPE_AC_UNI_QUEUE_SET_GRN_RESUME(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x3, value, PPE_AC_UNI_QUEUE_CFG_W3_GRN_RESUME)
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+
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+/* PPE multicast queue (256-299) configurations. */
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+#define PPE_AC_MUL_QUEUE_CFG_TBL_ADDR 0x84a000
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+#define PPE_AC_MUL_QUEUE_CFG_TBL_NUM 44
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+#define PPE_AC_MUL_QUEUE_CFG_TBL_INC 0x10
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+#define PPE_AC_MUL_QUEUE_CFG_W0_EN BIT(0)
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+#define PPE_AC_MUL_QUEUE_CFG_W0_FC_EN BIT(1)
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+#define PPE_AC_MUL_QUEUE_CFG_W0_COLOR_AWARE BIT(2)
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+#define PPE_AC_MUL_QUEUE_CFG_W0_GRP_ID GENMASK(4, 3)
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+#define PPE_AC_MUL_QUEUE_CFG_W0_PRE_LIMIT GENMASK(15, 5)
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+#define PPE_AC_MUL_QUEUE_CFG_W0_THRESHOLD GENMASK(26, 16)
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+#define PPE_AC_MUL_QUEUE_CFG_W2_RESUME GENMASK(17, 7)
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+
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+#define PPE_AC_MUL_QUEUE_SET_EN(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_MUL_QUEUE_CFG_W0_EN)
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+#define PPE_AC_MUL_QUEUE_SET_GRN_GRP_ID(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_MUL_QUEUE_CFG_W0_GRP_ID)
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+#define PPE_AC_MUL_QUEUE_SET_GRN_PRE_LIMIT(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_MUL_QUEUE_CFG_W0_PRE_LIMIT)
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+#define PPE_AC_MUL_QUEUE_SET_GRN_THRESHOLD(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_AC_MUL_QUEUE_CFG_W0_THRESHOLD)
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+#define PPE_AC_MUL_QUEUE_SET_GRN_RESUME(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x2, value, PPE_AC_MUL_QUEUE_CFG_W2_RESUME)
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+
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+/* PPE admission control group (0-3) configurations */
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+#define PPE_AC_GRP_CFG_TBL_ADDR 0x84c000
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+#define PPE_AC_GRP_CFG_TBL_NUM 0x4
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+#define PPE_AC_GRP_CFG_TBL_INC 0x10
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+#define PPE_AC_GRP_W0_AC_EN BIT(0)
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+#define PPE_AC_GRP_W0_AC_FC_EN BIT(1)
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+#define PPE_AC_GRP_W0_COLOR_AWARE BIT(2)
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+#define PPE_AC_GRP_W0_THRESHOLD_LOW GENMASK(31, 25)
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+#define PPE_AC_GRP_W1_THRESHOLD_HIGH GENMASK(3, 0)
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+#define PPE_AC_GRP_W1_BUF_LIMIT GENMASK(14, 4)
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+#define PPE_AC_GRP_W2_RESUME_GRN GENMASK(15, 5)
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+#define PPE_AC_GRP_W2_PRE_ALLOC GENMASK(26, 16)
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+
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+#define PPE_AC_GRP_SET_BUF_LIMIT(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_AC_GRP_W1_BUF_LIMIT)
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+
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+#define PPE_ENQ_OPR_TBL_ADDR 0x85c000
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+#define PPE_ENQ_OPR_TBL_NUM 300
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+#define PPE_ENQ_OPR_TBL_INC 0x10
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+#define PPE_ENQ_OPR_TBL_ENQ_DISABLE BIT(0)
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+
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#endif
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