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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
348 lines
10 KiB
Diff
348 lines
10 KiB
Diff
From a29ee27a42fc208ef1cd99f5014d57dbfe1af3dd Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Tue, 26 Dec 2023 17:11:35 +0800
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Subject: [PATCH 18/50] net: ethernet: qualcomm: Add PPE driver for IPQ9574 SoC
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The PPE (Packet Process Engine) hardware block is available
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on Qualcomm IPQ SoC that support PPE architecture, such as
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IPQ9574.
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The PPE in IPQ9574 includes six integrated ethernet MAC
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(for 6 PPE ports), buffer management, queue management and
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scheduler functions. The MACs can connect with the external
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PHY or switch devices using the UNIPHY PCS block available
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in the SoC.
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The PPE also includes various packet processing offload
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capabilities such as L3 routing and L2 bridging, VLAN and
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tunnel processing offload. It also includes Ethernet DMA (EDMA)
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function for transferring packets between ARM cores and PPE
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ethernet ports.
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This patch adds the base source files and Makefiles for the PPE
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driver such as platform driver registration, clock initialization,
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and PPE reset routines.
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Change-Id: I73166b5d4bb7e3c42ec6e0ac178a75528a25ef30
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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drivers/net/ethernet/qualcomm/Kconfig | 15 ++
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drivers/net/ethernet/qualcomm/Makefile | 1 +
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drivers/net/ethernet/qualcomm/ppe/Makefile | 7 +
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drivers/net/ethernet/qualcomm/ppe/ppe.c | 225 +++++++++++++++++++++
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drivers/net/ethernet/qualcomm/ppe/ppe.h | 36 ++++
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5 files changed, 284 insertions(+)
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create mode 100644 drivers/net/ethernet/qualcomm/ppe/Makefile
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create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe.c
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create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe.h
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--- a/drivers/net/ethernet/qualcomm/Kconfig
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+++ b/drivers/net/ethernet/qualcomm/Kconfig
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@@ -61,6 +61,21 @@ config QCOM_EMAC
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low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
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Precision Clock Synchronization Protocol.
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+config QCOM_PPE
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+ tristate "Qualcomm Technologies, Inc. PPE Ethernet support"
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+ depends on HAS_IOMEM && OF
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+ depends on COMMON_CLK
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+ select REGMAP_MMIO
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+ help
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+ This driver supports the Qualcomm Technologies, Inc. packet
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+ process engine (PPE) available with IPQ SoC. The PPE houses
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+ the ethernet MACs, Ethernet DMA (EDMA) and switch core that
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+ supports L3 flow offload, L2 switch function, RSS and tunnel
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+ offload.
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+
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+ To compile this driver as a module, choose M here. The module
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+ will be called qcom-ppe.
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+
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source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
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endif # NET_VENDOR_QUALCOMM
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--- a/drivers/net/ethernet/qualcomm/Makefile
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+++ b/drivers/net/ethernet/qualcomm/Makefile
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@@ -11,4 +11,5 @@ qcauart-objs := qca_uart.o
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obj-y += emac/
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+obj-$(CONFIG_QCOM_PPE) += ppe/
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obj-$(CONFIG_RMNET) += rmnet/
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--- /dev/null
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+++ b/drivers/net/ethernet/qualcomm/ppe/Makefile
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@@ -0,0 +1,7 @@
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+# SPDX-License-Identifier: GPL-2.0-only
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+#
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+# Makefile for the device driver of PPE (Packet Process Engine) in IPQ SoC
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+#
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+
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+obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o
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+qcom-ppe-objs := ppe.o
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--- /dev/null
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe.c
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@@ -0,0 +1,225 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+/* PPE platform device probe, DTSI parser and PPE clock initializations. */
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+
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+#include <linux/clk.h>
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+#include <linux/interconnect.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+#include <linux/reset.h>
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+
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+#include "ppe.h"
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+
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+#define PPE_PORT_MAX 8
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+#define PPE_CLK_RATE 353000000
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+
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+/* ICC clocks for enabling PPE device. The avg and peak with value 0
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+ * will be decided by the clock rate of PPE.
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+ */
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+static const struct icc_bulk_data ppe_icc_data[] = {
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+ {
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+ .name = "ppe",
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+ .avg_bw = 0,
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+ .peak_bw = 0,
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+ },
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+ {
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+ .name = "ppe_cfg",
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+ .avg_bw = 0,
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+ .peak_bw = 0,
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+ },
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+ {
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+ .name = "qos_gen",
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+ .avg_bw = 6000,
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+ .peak_bw = 6000,
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+ },
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+ {
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+ .name = "timeout_ref",
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+ .avg_bw = 6000,
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+ .peak_bw = 6000,
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+ },
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+ {
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+ .name = "nssnoc_memnoc",
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+ .avg_bw = 533333,
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+ .peak_bw = 533333,
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+ },
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+ {
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+ .name = "memnoc_nssnoc",
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+ .avg_bw = 533333,
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+ .peak_bw = 533333,
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+ },
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+ {
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+ .name = "memnoc_nssnoc_1",
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+ .avg_bw = 533333,
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+ .peak_bw = 533333,
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+ },
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+};
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+
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+static const struct regmap_range ppe_readable_ranges[] = {
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+ regmap_reg_range(0x0, 0x1ff), /* Global */
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+ regmap_reg_range(0x400, 0x5ff), /* LPI CSR */
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+ regmap_reg_range(0x1000, 0x11ff), /* GMAC0 */
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+ regmap_reg_range(0x1200, 0x13ff), /* GMAC1 */
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+ regmap_reg_range(0x1400, 0x15ff), /* GMAC2 */
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+ regmap_reg_range(0x1600, 0x17ff), /* GMAC3 */
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+ regmap_reg_range(0x1800, 0x19ff), /* GMAC4 */
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+ regmap_reg_range(0x1a00, 0x1bff), /* GMAC5 */
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+ regmap_reg_range(0xb000, 0xefff), /* PRX CSR */
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+ regmap_reg_range(0xf000, 0x1efff), /* IPE */
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+ regmap_reg_range(0x20000, 0x5ffff), /* PTX CSR */
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+ regmap_reg_range(0x60000, 0x9ffff), /* IPE L2 CSR */
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+ regmap_reg_range(0xb0000, 0xeffff), /* IPO CSR */
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+ regmap_reg_range(0x100000, 0x17ffff), /* IPE PC */
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+ regmap_reg_range(0x180000, 0x1bffff), /* PRE IPO CSR */
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+ regmap_reg_range(0x1d0000, 0x1dffff), /* Tunnel parser */
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+ regmap_reg_range(0x1e0000, 0x1effff), /* Ingress parse */
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+ regmap_reg_range(0x200000, 0x2fffff), /* IPE L3 */
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+ regmap_reg_range(0x300000, 0x3fffff), /* IPE tunnel */
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+ regmap_reg_range(0x400000, 0x4fffff), /* Scheduler */
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+ regmap_reg_range(0x500000, 0x503fff), /* XGMAC0 */
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+ regmap_reg_range(0x504000, 0x507fff), /* XGMAC1 */
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+ regmap_reg_range(0x508000, 0x50bfff), /* XGMAC2 */
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+ regmap_reg_range(0x50c000, 0x50ffff), /* XGMAC3 */
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+ regmap_reg_range(0x510000, 0x513fff), /* XGMAC4 */
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+ regmap_reg_range(0x514000, 0x517fff), /* XGMAC5 */
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+ regmap_reg_range(0x600000, 0x6fffff), /* BM */
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+ regmap_reg_range(0x800000, 0x9fffff), /* QM */
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+ regmap_reg_range(0xb00000, 0xbef800), /* EDMA */
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+};
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+
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+static const struct regmap_access_table ppe_reg_table = {
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+ .yes_ranges = ppe_readable_ranges,
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+ .n_yes_ranges = ARRAY_SIZE(ppe_readable_ranges),
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+};
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+
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+static const struct regmap_config regmap_config_ipq9574 = {
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+ .reg_bits = 32,
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+ .reg_stride = 4,
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+ .val_bits = 32,
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+ .rd_table = &ppe_reg_table,
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+ .wr_table = &ppe_reg_table,
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+ .max_register = 0xbef800,
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+ .fast_io = true,
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+};
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+
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+static int ppe_clock_init_and_reset(struct ppe_device *ppe_dev)
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+{
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+ unsigned long ppe_rate = ppe_dev->clk_rate;
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+ struct device *dev = ppe_dev->dev;
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+ struct reset_control *rstc;
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+ struct clk_bulk_data *clks;
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+ struct clk *clk;
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+ int ret, i;
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+
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+ for (i = 0; i < ppe_dev->num_icc_paths; i++) {
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+ ppe_dev->icc_paths[i].name = ppe_icc_data[i].name;
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+ ppe_dev->icc_paths[i].avg_bw = ppe_icc_data[i].avg_bw ? :
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+ Bps_to_icc(ppe_rate);
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+ ppe_dev->icc_paths[i].peak_bw = ppe_icc_data[i].peak_bw ? :
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+ Bps_to_icc(ppe_rate);
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+ }
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+
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+ ret = devm_of_icc_bulk_get(dev, ppe_dev->num_icc_paths,
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+ ppe_dev->icc_paths);
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+ if (ret)
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+ return ret;
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+
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+ ret = icc_bulk_set_bw(ppe_dev->num_icc_paths, ppe_dev->icc_paths);
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+ if (ret)
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+ return ret;
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+
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+ /* PPE clocks take the same clock tree, which work on the same
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+ * clock rate. Setting the clock rate of "ppe" ensures the clock
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+ * rate of all PPE clocks configured as same.
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+ */
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+ clk = devm_clk_get(dev, "ppe");
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+ if (IS_ERR(clk))
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+ return PTR_ERR(clk);
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+
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+ ret = clk_set_rate(clk, ppe_rate);
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+ if (ret)
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+ return ret;
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+
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+ ret = devm_clk_bulk_get_all_enabled(dev, &clks);
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+ if (ret < 0)
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+ return ret;
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+
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+ rstc = devm_reset_control_get_exclusive(dev, NULL);
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+ if (IS_ERR(rstc))
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+ return PTR_ERR(rstc);
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+
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+ /* Reset PPE, the delay 100ms of assert and deassert is necessary
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+ * for resetting PPE.
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+ */
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+ ret = reset_control_assert(rstc);
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+ if (ret)
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+ return ret;
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+
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+ msleep(100);
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+ ret = reset_control_deassert(rstc);
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+ if (ret)
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+ return ret;
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+
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+ msleep(100);
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+
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+ return 0;
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+}
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+
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+static int qcom_ppe_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct ppe_device *ppe_dev;
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+ void __iomem *base;
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+ int ret, num_icc;
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+
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+ num_icc = ARRAY_SIZE(ppe_icc_data);
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+ ppe_dev = devm_kzalloc(dev,
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+ struct_size(ppe_dev, icc_paths, num_icc),
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+ GFP_KERNEL);
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+ if (!ppe_dev)
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+ return dev_err_probe(dev, -ENOMEM, "PPE alloc memory failed\n");
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+
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+ base = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(base))
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+ return dev_err_probe(dev, PTR_ERR(base), "PPE ioremap failed\n");
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+
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+ ppe_dev->regmap = devm_regmap_init_mmio(dev, base, ®map_config_ipq9574);
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+ if (IS_ERR(ppe_dev->regmap))
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+ return dev_err_probe(dev, PTR_ERR(ppe_dev->regmap),
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+ "PPE initialize regmap failed\n");
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+ ppe_dev->dev = dev;
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+ ppe_dev->clk_rate = PPE_CLK_RATE;
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+ ppe_dev->num_ports = PPE_PORT_MAX;
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+ ppe_dev->num_icc_paths = num_icc;
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+
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+ ret = ppe_clock_init_and_reset(ppe_dev);
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+ if (ret)
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+ return dev_err_probe(dev, ret, "PPE clock config failed\n");
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+
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+ platform_set_drvdata(pdev, ppe_dev);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id qcom_ppe_of_match[] = {
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+ { .compatible = "qcom,ipq9574-ppe" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, qcom_ppe_of_match);
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+
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+static struct platform_driver qcom_ppe_driver = {
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+ .driver = {
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+ .name = "qcom_ppe",
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+ .of_match_table = qcom_ppe_of_match,
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+ },
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+ .probe = qcom_ppe_probe,
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+};
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+module_platform_driver(qcom_ppe_driver);
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+
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+MODULE_LICENSE("GPL");
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+MODULE_DESCRIPTION("Qualcomm IPQ PPE driver");
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--- /dev/null
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe.h
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@@ -0,0 +1,36 @@
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+/* SPDX-License-Identifier: GPL-2.0-only
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+ *
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+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef __PPE_H__
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+#define __PPE_H__
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+
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+#include <linux/compiler.h>
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+#include <linux/interconnect.h>
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+
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+struct device;
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+struct regmap;
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+
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+/**
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+ * struct ppe_device - PPE device private data.
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+ * @dev: PPE device structure.
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+ * @regmap: PPE register map.
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+ * @clk_rate: PPE clock rate.
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+ * @num_ports: Number of PPE ports.
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+ * @num_icc_paths: Number of interconnect paths.
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+ * @icc_paths: Interconnect path array.
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+ *
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+ * PPE device is the instance of PPE hardware, which is used to
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+ * configure PPE packet process modules such as BM (buffer management),
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+ * QM (queue management), and scheduler.
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+ */
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+struct ppe_device {
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+ struct device *dev;
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+ struct regmap *regmap;
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+ unsigned long clk_rate;
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+ unsigned int num_ports;
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+ unsigned int num_icc_paths;
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+ struct icc_bulk_data icc_paths[] __counted_by(num_icc_paths);
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+};
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+#endif
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