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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
199 lines
5.9 KiB
Diff
199 lines
5.9 KiB
Diff
From fcd1c53b460aa39cfd15f842126af62b27a4fad5 Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Tue, 2 Apr 2024 18:28:42 +0800
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Subject: [PATCH 13/50] net: pcs: Add 2500BASEX interface mode support to IPQ
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UNIPHY PCS driver
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2500BASEX mode is used when PCS connects with QCA8386 switch in a fixed
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2500M link. It is also used when PCS connectes with QCA8081 PHY which
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works at 2500M link speed. In addition, it can be also used when PCS
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connects with a 2.5G SFP module.
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Change-Id: I3fe61113c1b3685debc20659736a9488216a029d
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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---
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drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 95 +++++++++++++++++++++++++++
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1 file changed, 95 insertions(+)
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--- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
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+++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
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@@ -25,6 +25,7 @@
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#define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4)
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#define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1)
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#define PCS_MODE_PSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x2)
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+#define PCS_MODE_SGMII_PLUS FIELD_PREP(PCS_MODE_SEL_MASK, 0x8)
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#define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10)
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#define PCS_MODE_AN_MODE BIT(0)
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@@ -282,6 +283,24 @@ static void ipq_unipcs_get_state_sgmii(s
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state->pause |= MLO_PAUSE_RX;
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}
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+static void ipq_unipcs_get_state_2500basex(struct ipq_uniphy_pcs *qunipcs,
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+ int channel,
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+ struct phylink_link_state *state)
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+{
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+ u32 val;
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+
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+ val = ipq_unipcs_reg_read32(qunipcs, PCS_CHANNEL_STS(channel));
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+
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+ state->link = !!(val & PCS_CHANNEL_LINK_STS);
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+
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+ if (!state->link)
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+ return;
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+
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+ state->speed = SPEED_2500;
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+ state->duplex = DUPLEX_FULL;
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+ state->pause |= MLO_PAUSE_TXRX_MASK;
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+}
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+
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static void ipq_unipcs_get_state_usxgmii(struct ipq_uniphy_pcs *qunipcs,
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struct phylink_link_state *state)
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{
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@@ -373,6 +392,12 @@ static int ipq_unipcs_config_mode(struct
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PCS_MODE_SEL_MASK | PCS_MODE_AN_MODE,
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PCS_MODE_PSGMII);
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break;
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ rate = 312500000;
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+ ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL,
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+ PCS_MODE_SEL_MASK,
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+ PCS_MODE_SGMII_PLUS);
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+ break;
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10GBASER:
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rate = 312500000;
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@@ -450,6 +475,22 @@ err:
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return ret;
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}
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+static int ipq_unipcs_config_2500basex(struct ipq_uniphy_pcs *qunipcs,
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+ phy_interface_t interface)
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+{
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+ int ret;
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+
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+ if (qunipcs->interface != interface) {
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+ ret = ipq_unipcs_config_mode(qunipcs, interface);
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+ if (ret)
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+ return ret;
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+
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+ qunipcs->interface = interface;
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+ }
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+
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+ return 0;
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+}
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+
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static int ipq_unipcs_config_usxgmii(struct ipq_uniphy_pcs *qunipcs,
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unsigned int neg_mode,
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phy_interface_t interface)
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@@ -522,6 +563,21 @@ static unsigned long ipq_unipcs_clock_ra
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return rate;
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}
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+static unsigned long ipq_unipcs_clock_rate_get_gmiiplus(int speed)
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+{
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+ unsigned long rate = 0;
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+
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+ switch (speed) {
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+ case SPEED_2500:
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+ rate = 312500000;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ return rate;
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+}
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+
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static unsigned long ipq_unipcs_clock_rate_get_xgmii(int speed)
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{
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unsigned long rate = 0;
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@@ -566,6 +622,9 @@ ipq_unipcs_link_up_clock_rate_set(struct
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case PHY_INTERFACE_MODE_PSGMII:
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rate = ipq_unipcs_clock_rate_get_gmii(speed);
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break;
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ rate = ipq_unipcs_clock_rate_get_gmiiplus(speed);
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+ break;
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10GBASER:
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rate = ipq_unipcs_clock_rate_get_xgmii(speed);
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@@ -627,6 +686,21 @@ pcs_adapter_reset:
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PCS_CHANNEL_ADPT_RESET);
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}
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+static void ipq_unipcs_link_up_config_2500basex(struct ipq_uniphy_pcs *qunipcs,
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+ int channel,
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+ int speed)
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+{
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+ /* 2500BASEX do not support autoneg and do not need to
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+ * configure PCS speed, only reset PCS adapter here.
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+ */
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+ ipq_unipcs_reg_modify32(qunipcs, PCS_CHANNEL_CTRL(channel),
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+ PCS_CHANNEL_ADPT_RESET,
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+ 0);
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+ ipq_unipcs_reg_modify32(qunipcs, PCS_CHANNEL_CTRL(channel),
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+ PCS_CHANNEL_ADPT_RESET,
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+ PCS_CHANNEL_ADPT_RESET);
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+}
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+
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static void ipq_unipcs_link_up_config_usxgmii(struct ipq_uniphy_pcs *qunipcs,
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int speed)
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{
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@@ -669,6 +743,17 @@ static void ipq_unipcs_link_up_config_us
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XPCS_USXG_ADPT_RESET);
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}
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+static int ipq_unipcs_validate(struct phylink_pcs *pcs,
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+ unsigned long *supported,
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+ const struct phylink_link_state *state)
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+{
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+ /* In-band autoneg is not supported for 2500BASEX */
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+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
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+ phylink_clear(supported, Autoneg);
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+
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+ return 0;
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+}
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+
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static void ipq_unipcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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@@ -682,6 +767,9 @@ static void ipq_unipcs_get_state(struct
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case PHY_INTERFACE_MODE_PSGMII:
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ipq_unipcs_get_state_sgmii(qunipcs, channel, state);
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break;
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ ipq_unipcs_get_state_2500basex(qunipcs, channel, state);
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+ break;
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case PHY_INTERFACE_MODE_USXGMII:
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ipq_unipcs_get_state_usxgmii(qunipcs, state);
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break;
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@@ -716,6 +804,8 @@ static int ipq_unipcs_config(struct phyl
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case PHY_INTERFACE_MODE_PSGMII:
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return ipq_unipcs_config_sgmii(qunipcs, channel,
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neg_mode, interface);
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ return ipq_unipcs_config_2500basex(qunipcs, interface);
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case PHY_INTERFACE_MODE_USXGMII:
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return ipq_unipcs_config_usxgmii(qunipcs,
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neg_mode, interface);
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@@ -748,6 +838,10 @@ static void ipq_unipcs_link_up(struct ph
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ipq_unipcs_link_up_config_sgmii(qunipcs, channel,
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neg_mode, speed);
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break;
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ ipq_unipcs_link_up_config_2500basex(qunipcs,
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+ channel, speed);
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+ break;
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case PHY_INTERFACE_MODE_USXGMII:
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ipq_unipcs_link_up_config_usxgmii(qunipcs, speed);
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break;
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@@ -761,6 +855,7 @@ static void ipq_unipcs_link_up(struct ph
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}
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static const struct phylink_pcs_ops ipq_unipcs_phylink_ops = {
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+ .pcs_validate = ipq_unipcs_validate,
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.pcs_get_state = ipq_unipcs_get_state,
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.pcs_config = ipq_unipcs_config,
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.pcs_link_up = ipq_unipcs_link_up,
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