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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
121 lines
3.4 KiB
Diff
121 lines
3.4 KiB
Diff
From f23eb497c891985126a065f950bc61e9c404bb12 Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Wed, 6 Mar 2024 17:40:52 +0800
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Subject: [PATCH 12/50] net: pcs: Add 10GBASER interface mode support to IPQ
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UNIPHY PCS driver
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10GBASER mode is used when PCS connects with a 10G SFP module.
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Change-Id: Ifc3c3bb23811807a9b34e88771aab2c830c2327c
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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---
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drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 48 +++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
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+++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
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@@ -57,6 +57,9 @@
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FIELD_PREP(GENMASK(9, 2), \
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FIELD_GET(XPCS_INDIRECT_ADDR_L, reg)))
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+#define XPCS_10GBASER_STS 0x30020
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+#define XPCS_10GBASER_LINK_STS BIT(12)
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+
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#define XPCS_DIG_CTRL 0x38000
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#define XPCS_USXG_ADPT_RESET BIT(10)
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#define XPCS_USXG_EN BIT(9)
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@@ -320,6 +323,23 @@ static void ipq_unipcs_get_state_usxgmii
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state->duplex = DUPLEX_HALF;
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}
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+static void ipq_unipcs_get_state_10gbaser(struct ipq_uniphy_pcs *qunipcs,
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+ struct phylink_link_state *state)
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+{
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+ u32 val;
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+
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+ val = ipq_unipcs_reg_read32(qunipcs, XPCS_10GBASER_STS);
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+
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+ state->link = !!(val & XPCS_10GBASER_LINK_STS);
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+
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+ if (!state->link)
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+ return;
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+
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+ state->speed = SPEED_10000;
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+ state->duplex = DUPLEX_FULL;
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+ state->pause |= MLO_PAUSE_TXRX_MASK;
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+}
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+
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static int ipq_unipcs_config_mode(struct ipq_uniphy_pcs *qunipcs,
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phy_interface_t interface)
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{
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@@ -354,6 +374,7 @@ static int ipq_unipcs_config_mode(struct
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PCS_MODE_PSGMII);
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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rate = 312500000;
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ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL,
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PCS_MODE_SEL_MASK,
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@@ -461,6 +482,25 @@ static int ipq_unipcs_config_usxgmii(str
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return 0;
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}
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+static int ipq_unipcs_config_10gbaser(struct ipq_uniphy_pcs *qunipcs,
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+ phy_interface_t interface)
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+{
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+ int ret;
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+
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+ if (qunipcs->interface != interface) {
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+ ret = ipq_unipcs_config_mode(qunipcs, interface);
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+ if (ret)
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+ return ret;
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+
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+ /* Deassert XPCS */
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+ reset_control_deassert(qunipcs->reset[XPCS_RESET]);
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+
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+ qunipcs->interface = interface;
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+ }
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+
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+ return 0;
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+}
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+
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static unsigned long ipq_unipcs_clock_rate_get_gmii(int speed)
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{
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unsigned long rate = 0;
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@@ -527,6 +567,7 @@ ipq_unipcs_link_up_clock_rate_set(struct
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rate = ipq_unipcs_clock_rate_get_gmii(speed);
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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rate = ipq_unipcs_clock_rate_get_xgmii(speed);
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break;
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default:
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@@ -644,6 +685,9 @@ static void ipq_unipcs_get_state(struct
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case PHY_INTERFACE_MODE_USXGMII:
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ipq_unipcs_get_state_usxgmii(qunipcs, state);
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break;
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ ipq_unipcs_get_state_10gbaser(qunipcs, state);
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+ break;
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default:
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break;
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}
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@@ -675,6 +719,8 @@ static int ipq_unipcs_config(struct phyl
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case PHY_INTERFACE_MODE_USXGMII:
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return ipq_unipcs_config_usxgmii(qunipcs,
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neg_mode, interface);
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ return ipq_unipcs_config_10gbaser(qunipcs, interface);
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default:
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dev_err(qunipcs->dev,
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"interface %s not supported\n", phy_modes(interface));
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@@ -705,6 +751,8 @@ static void ipq_unipcs_link_up(struct ph
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case PHY_INTERFACE_MODE_USXGMII:
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ipq_unipcs_link_up_config_usxgmii(qunipcs, speed);
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break;
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ break;
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default:
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dev_err(qunipcs->dev,
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"interface %s not supported\n", phy_modes(interface));
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