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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
141 lines
4.4 KiB
Diff
141 lines
4.4 KiB
Diff
From 9d0e22124d6f3ca901626dd5537b36c7c0c97812 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Mon, 29 Jan 2024 10:51:38 +0800
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Subject: [PATCH 06/50] net: phy: qca808x: Add QCA8084 probe function
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Add the PHY package probe function. The MDIO slave address of
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PHY, PCS and XPCS can be optionally customized by configuring
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the PHY package level register.
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In addition, enable system clock of PHY and de-assert PHY in
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the probe function so that the register of PHY device can be
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accessed, and the features of PHY can be acquired.
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Change-Id: I2251b9c5c398a21a4ef547a727189a934ad3a44c
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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drivers/net/phy/qcom/qca808x.c | 91 ++++++++++++++++++++++++++++++++++
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1 file changed, 91 insertions(+)
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--- a/drivers/net/phy/qcom/qca808x.c
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+++ b/drivers/net/phy/qcom/qca808x.c
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@@ -2,6 +2,8 @@
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#include <linux/phy.h>
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#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/clk.h>
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#include "qcom.h"
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@@ -127,6 +129,21 @@
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#define QCA8084_MII_SW_ADDR_MASK GENMASK(31, 24)
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#define QCA8084_MII_REG_DATA_UPPER_16_BITS BIT(1)
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+/* QCA8084 integrates 4 PHYs, PCS0 and PCS1(includes PCS and XPCS). */
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+#define QCA8084_MDIO_DEVICE_NUM 7
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+
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+#define QCA8084_PCS_CFG 0xc90f014
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+#define QCA8084_PCS_ADDR0_MASK GENMASK(4, 0)
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+#define QCA8084_PCS_ADDR1_MASK GENMASK(9, 5)
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+#define QCA8084_PCS_ADDR2_MASK GENMASK(14, 10)
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+
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+#define QCA8084_EPHY_CFG 0xc90f018
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+#define QCA8084_EPHY_ADDR0_MASK GENMASK(4, 0)
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+#define QCA8084_EPHY_ADDR1_MASK GENMASK(9, 5)
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+#define QCA8084_EPHY_ADDR2_MASK GENMASK(14, 10)
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+#define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15)
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+#define QCA8084_EPHY_LDO_EN GENMASK(21, 20)
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+
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MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
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MODULE_LICENSE("GPL");
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@@ -836,6 +853,79 @@ static void qca8084_link_change_notify(s
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QCA8084_IPG_10_TO_11_EN : 0);
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}
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+static int qca8084_phy_package_probe_once(struct phy_device *phydev)
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+{
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+ int addr[QCA8084_MDIO_DEVICE_NUM] = {0, 1, 2, 3, 4, 5, 6};
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+ struct phy_package_shared *shared = phydev->shared;
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+ int ret, clear, set;
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+
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+ /* Program the MDIO address of PHY and PCS optionally, the MDIO
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+ * address 0-6 is used for PHY and PCS MDIO devices by default.
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+ */
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+ ret = of_property_read_u32_array(shared->np,
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+ "qcom,phy-addr-fixup",
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+ addr, ARRAY_SIZE(addr));
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+ if (ret && ret != -EINVAL)
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+ return ret;
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+
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+ /* Configure the MDIO addresses for the four PHY devices. */
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+ clear = QCA8084_EPHY_ADDR0_MASK | QCA8084_EPHY_ADDR1_MASK |
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+ QCA8084_EPHY_ADDR2_MASK | QCA8084_EPHY_ADDR3_MASK;
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+ set = FIELD_PREP(QCA8084_EPHY_ADDR0_MASK, addr[0]);
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+ set |= FIELD_PREP(QCA8084_EPHY_ADDR1_MASK, addr[1]);
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+ set |= FIELD_PREP(QCA8084_EPHY_ADDR2_MASK, addr[2]);
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+ set |= FIELD_PREP(QCA8084_EPHY_ADDR3_MASK, addr[3]);
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+
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+ ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, clear, set);
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+ if (ret)
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+ return ret;
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+
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+ /* Configure the MDIO addresses for PCS0 and PCS1 including
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+ * PCS and XPCS.
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+ */
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+ clear = QCA8084_PCS_ADDR0_MASK | QCA8084_PCS_ADDR1_MASK |
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+ QCA8084_PCS_ADDR2_MASK;
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+ set = FIELD_PREP(QCA8084_PCS_ADDR0_MASK, addr[4]);
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+ set |= FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]);
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+ set |= FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6]);
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+
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+ return qca8084_mii_modify(phydev, QCA8084_PCS_CFG, clear, set);
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+}
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+
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+static int qca8084_probe(struct phy_device *phydev)
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+{
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+ struct device *dev = &phydev->mdio.dev;
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+ struct reset_control *rstc;
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+ struct clk *clk;
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+ int ret;
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+
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+ ret = devm_of_phy_package_join(dev, phydev, 0);
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+ if (ret)
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+ return ret;
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+
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+ if (phy_package_probe_once(phydev)) {
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+ ret = qca8084_phy_package_probe_once(phydev);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ /* Enable clock of PHY device, so that the PHY register
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+ * can be accessed to get PHY features.
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+ */
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+ clk = devm_clk_get_enabled(dev, NULL);
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+ if (IS_ERR(clk))
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+ return dev_err_probe(dev, PTR_ERR(clk),
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+ "Enable PHY clock failed\n");
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+
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+ /* De-assert PHY reset after the clock of PHY enabled. */
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+ rstc = devm_reset_control_get_exclusive(dev, NULL);
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+ if (IS_ERR(rstc))
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+ return dev_err_probe(dev, PTR_ERR(rstc),
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+ "Get PHY reset failed\n");
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+
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+ return reset_control_deassert(rstc);
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+}
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+
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static struct phy_driver qca808x_driver[] = {
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{
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/* Qualcomm QCA8081 */
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@@ -886,6 +976,7 @@ static struct phy_driver qca808x_driver[
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.cable_test_get_status = qca808x_cable_test_get_status,
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.config_init = qca8084_config_init,
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.link_change_notify = qca8084_link_change_notify,
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+ .probe = qca8084_probe,
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}, };
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module_phy_driver(qca808x_driver);
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