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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
134 lines
4.4 KiB
Diff
134 lines
4.4 KiB
Diff
From 9dec04efa81322029e210281b1753a2eb5279e27 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Thu, 6 Apr 2023 18:09:07 +0800
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Subject: [PATCH 02/50] net: phy: qca808x: Add QCA8084 ethernet phy support
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Add QCA8084 Quad-PHY support, which is a four-port PHY with
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maximum link capability of 2.5 Gbps. The features of each port
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are almost same as QCA8081. The slave seed and fast retrain
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configs are not needed for QCA8084. It includes two PCSes.
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PCS0 of QCA8084 supports the interface modes:
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PHY_INTERFACE_MODE_2500BASEX and PHY_INTERFACE_MODE_SGMII.
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PCS1 of QCA8084 supports the interface modes:
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PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and
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PHY_INTERFACE_MODE_SGMII.
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The additional CDT configurations needed for QCA8084 compared
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with QCA8081.
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Change-Id: I12555fa70662682474ab4432204405b5e752fef6
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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drivers/net/phy/qcom/qca808x.c | 62 ++++++++++++++++++++++++++++++++--
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1 file changed, 60 insertions(+), 2 deletions(-)
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--- a/drivers/net/phy/qcom/qca808x.c
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+++ b/drivers/net/phy/qcom/qca808x.c
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@@ -86,9 +86,16 @@
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#define QCA8081_PHY_FIFO_RSTN BIT(11)
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#define QCA8081_PHY_ID 0x004dd101
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+#define QCA8084_PHY_ID 0x004dd180
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+
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+#define QCA8084_MMD3_CDT_PULSE_CTRL 0x8075
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+#define QCA8084_CDT_PULSE_THRESH_VAL 0xa060
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+
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+#define QCA8084_MMD3_CDT_NEAR_CTRL 0x807f
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+#define QCA8084_CDT_NEAR_BYPASS BIT(15)
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MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
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-MODULE_AUTHOR("Matus Ujhelyi");
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+MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
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MODULE_LICENSE("GPL");
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struct qca808x_priv {
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@@ -153,7 +160,9 @@ static bool qca808x_is_prefer_master(str
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static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
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{
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- return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
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+ return phydev_id_compare(phydev, QCA8081_PHY_ID) &&
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+ linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
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+ phydev->supported);
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}
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static bool qca808x_is_1g_only(struct phy_device *phydev)
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@@ -273,6 +282,23 @@ static int qca808x_read_status(struct ph
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return ret;
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if (phydev->link) {
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+ /* There are two PCSes available for QCA8084, which support
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+ * the following interface modes.
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+ *
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+ * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all
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+ * available 4 ports, which is for all link speeds.
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+ *
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+ * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the
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+ * fourth port, which is only for the link speed 2500M same
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+ * as QCA8081.
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+ *
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+ * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth
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+ * port, which is for the link speed 10M, 100M and 1000M same
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+ * as QCA8081.
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+ */
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+ if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
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+ return 0;
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+
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if (phydev->speed == SPEED_2500)
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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else
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@@ -352,6 +378,18 @@ static int qca808x_cable_test_start(stru
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
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+ if (phydev_id_compare(phydev, QCA8084_PHY_ID)) {
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+ /* Adjust the positive and negative pulse thereshold of CDT. */
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+ phy_write_mmd(phydev, MDIO_MMD_PCS,
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+ QCA8084_MMD3_CDT_PULSE_CTRL,
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+ QCA8084_CDT_PULSE_THRESH_VAL);
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+
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+ /* Disable the near bypass of CDT. */
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+ phy_modify_mmd(phydev, MDIO_MMD_PCS,
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+ QCA8084_MMD3_CDT_NEAR_CTRL,
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+ QCA8084_CDT_NEAR_BYPASS, 0);
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+ }
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+
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return 0;
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}
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@@ -651,12 +689,32 @@ static struct phy_driver qca808x_driver[
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.led_hw_control_set = qca808x_led_hw_control_set,
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.led_hw_control_get = qca808x_led_hw_control_get,
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.led_polarity_set = qca808x_led_polarity_set,
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+}, {
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+ /* Qualcomm QCA8084 */
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+ PHY_ID_MATCH_MODEL(QCA8084_PHY_ID),
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+ .name = "Qualcomm QCA8084",
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+ .flags = PHY_POLL_CABLE_TEST,
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+ .config_intr = at803x_config_intr,
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+ .handle_interrupt = at803x_handle_interrupt,
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+ .get_tunable = at803x_get_tunable,
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+ .set_tunable = at803x_set_tunable,
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+ .set_wol = at803x_set_wol,
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+ .get_wol = at803x_get_wol,
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+ .get_features = qca808x_get_features,
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+ .config_aneg = qca808x_config_aneg,
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+ .suspend = genphy_suspend,
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+ .resume = genphy_resume,
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+ .read_status = qca808x_read_status,
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+ .soft_reset = qca808x_soft_reset,
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+ .cable_test_start = qca808x_cable_test_start,
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+ .cable_test_get_status = qca808x_cable_test_get_status,
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}, };
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module_phy_driver(qca808x_driver);
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static struct mdio_device_id __maybe_unused qca808x_tbl[] = {
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{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
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+ { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) },
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{ }
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};
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