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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
245 lines
8.6 KiB
Diff
245 lines
8.6 KiB
Diff
From 9e76817056937645205f23ee91e762d5cff5e848 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Mon, 29 Jan 2024 17:57:20 +0800
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Subject: [PATCH 01/50] dt-bindings: net: Document Qualcomm QCA8084 PHY package
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QCA8084 is quad PHY chip, which integrates 4 PHYs, 2 PCS
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interfaces (PCS0 and PCS1) and clock controller, which can
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also be integrated to the switch chip named as QCA8386.
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1. MDIO address of 4 PHYs, 2 PCS and 1 XPCS (PCS1 includes
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PCS and XPCS, PCS0 includes PCS) can be configured.
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2. The package mode of PHY is optionally configured for the
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interface mode of two PCSes working correctly.
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3. The package level clock and reset need to be initialized.
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4. The clock and reset per PHY device need to be initialized
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so that the PHY register can be accessed.
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Change-Id: Idb2338d2673152cbd3c57e95968faa59e9d4a80f
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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.../devicetree/bindings/net/qcom,qca8084.yaml | 198 ++++++++++++++++++
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include/dt-bindings/net/qcom,qca808x.h | 14 ++
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2 files changed, 212 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/net/qcom,qca8084.yaml
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create mode 100644 include/dt-bindings/net/qcom,qca808x.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/qcom,qca8084.yaml
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@@ -0,0 +1,198 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/net/qcom,qca8084.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm QCA8084 Ethernet Quad PHY
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+
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+maintainers:
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+ - Luo Jie <quic_luoj@quicinc.com>
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+
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+description:
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+ Qualcomm QCA8084 is a four-port Ethernet transceiver, the
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+ Ethernet port supports link speed 10/100/1000/2500 Mbps.
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+ There are two PCSes (PCS0 and PCS1) integrated in the PHY
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+ package, PCS1 includes XPCS and PCS to support the interface
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+ mode 10G-QXGMII and SGMII, PCS0 includes a PCS to support the
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+ interface mode SGMII only. There is also a clock controller
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+ integrated in the PHY package. This four-port Ethernet
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+ transceiver can also be integrated to the switch chip named
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+ as QCA8386. The PHY package mode needs to be configured as the
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+ correct value to apply the interface mode of two PCSes as
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+ mentioned below.
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+
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+ QCA8084 expects an input reference clock 50 MHZ as the clock
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+ source of the integrated clock controller, the integrated
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+ clock controller supplies the clocks and resets to the
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+ integrated PHY, PCS and PHY package.
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+
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+ - |
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+ +--| |--+-------------------+--| |--+
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+ | PCS1 |<------------+---->| PCS0 |
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+ +-------+ | +-------+
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+ | | |
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+ Ref 50M clk +--------+ | |
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+ ------------>| | clk & rst | |
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+ GPIO Reset |QCA8K_CC+------------+ |
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+ ------------>| | | |
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+ +--------+ | |
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+ | V |
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+ +--------+--------+--------+--------+
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+ | PHY0 | PHY1 | PHY2 | PHY3 |
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+ +--------+--------+--------+--------+
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+
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+$ref: ethernet-phy-package.yaml#
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+
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+properties:
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+ compatible:
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+ const: qcom,qca8084-package
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+
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+ clocks:
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+ description: PHY package level initial common clocks, which are
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+ needed to be enabled after GPIO reset on the PHY package, these
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+ clocks are supplied from the PHY integrated clock controller
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+ (QCA8K-CC).
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+ items:
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+ - description: APB bridge clock
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+ - description: AHB clock
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+ - description: Security control clock
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+ - description: TLMM clock
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+ - description: TLMM AHB clock
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+ - description: CNOC AHB clock
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+ - description: MDIO AHB clock
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+
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+ clock-names:
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+ items:
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+ - const: apb_bridge
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+ - const: ahb
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+ - const: sec_ctrl_ahb
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+ - const: tlmm
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+ - const: tlmm_ahb
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+ - const: cnoc_ahb
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+ - const: mdio_ahb
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+
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+ resets:
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+ description: PHY package level initial common reset, which are
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+ needed to be deasserted after GPIO reset on the PHY package,
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+ this reset is provided by the PHY integrated clock controller
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+ to do PHY DSP reset.
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+ maxItems: 1
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+
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+ qcom,package-mode:
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+ description: |
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+ The package mode of PHY supports to be configured as 3 modes
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+ to apply the combinations of interface mode of two PCSes
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+ correctly. This value should use one of the values defined in
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+ dt-bindings/net/qcom,qca808x.h. The package mode 10G-QXGMII of
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+ Quad PHY is used by default.
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+
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+ package mode PCS1 PCS0
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+ phy mode (0) 10G-QXGMII for not used
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+ PHY0-PHY3
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+
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+ switch mode (1) SGMII for SGMII for
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+ switch MAC0 switch MAC5 (optional)
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+
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+ switch bypass MAC5 (2) SGMII for SGMII for
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+ switch MAC0 PHY3
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+ $ref: /schemas/types.yaml#/definitions/uint32
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+ enum: [0, 1, 2]
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+ default: 0
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+
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+ qcom,phy-addr-fixup:
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+ description: MDIO address for PHY0-PHY3, PCS0 and PCS1 including
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+ PCS and XPCS, which can be optionally customized by programming
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+ the security control register of PHY package. The hardware default
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+ MDIO address of PHY0-PHY3, PCS0 and PCS1 including PCS and XPCS is
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+ 0-6.
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+ $ref: /schemas/types.yaml#/definitions/uint32-array
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+ minItems: 7
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+ maxItems: 7
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+
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+patternProperties:
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+ ^ethernet-phy(@[a-f0-9]+)?$:
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+ $ref: ethernet-phy.yaml#
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+
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+ properties:
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+ compatible:
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+ const: ethernet-phy-id004d.d180
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+
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+ required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - resets
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+
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+ unevaluatedProperties: false
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+
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+required:
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+ - compatible
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+ - clocks
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+ - clock-names
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+ - resets
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,qca8k-nsscc.h>
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+ #include <dt-bindings/net/qcom,qca808x.h>
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+ #include <dt-bindings/reset/qcom,qca8k-nsscc.h>
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethernet-phy-package@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "qcom,qca8084-package";
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+ reg = <1>;
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+ clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
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+ <&qca8k_nsscc NSS_CC_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_TLMM_CLK>,
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+ <&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>;
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+ clock-names = "apb_bridge",
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+ "ahb",
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+ "sec_ctrl_ahb",
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+ "tlmm",
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+ "tlmm_ahb",
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+ "cnoc_ahb",
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+ "mdio_ahb";
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY_FULL_ARES>;
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+ qcom,package-mode = <QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC>;
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+ qcom,phy-addr-fixup = <1 2 3 4 5 6 7>;
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+
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+ ethernet-phy@1 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <1>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>;
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+ };
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+
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+ ethernet-phy@2 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <2>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>;
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+ };
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+
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+ ethernet-phy@3 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <3>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>;
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+ };
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+
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+ ethernet-phy@4 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <4>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_ARES>;
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+ };
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+ };
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+ };
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--- /dev/null
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+++ b/include/dt-bindings/net/qcom,qca808x.h
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@@ -0,0 +1,14 @@
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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+/*
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+ * Device Tree constants for the Qualcomm QCA808X PHYs
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+ */
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+
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+#ifndef _DT_BINDINGS_QCOM_QCA808X_H
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+#define _DT_BINDINGS_QCOM_QCA808X_H
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+
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+/* PHY package modes of QCA8084 to apply the interface modes of two PCSes. */
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+#define QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED 0
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+#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC 1
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+#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_PHY 2
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+
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+#endif
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