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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
106 lines
2.8 KiB
Diff
106 lines
2.8 KiB
Diff
From b36074357baf2794c825ea1c145de1d22b15380b Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Fri, 20 Oct 2023 11:49:39 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq9574: populate the opp table based on
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the eFuse
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IPQ95xx SoCs have different OPPs available for the CPU based on
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SoC variant. This can be determined from an eFuse register
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present in the silicon.
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Add support to read the eFuse and populate the OPPs based on it.
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Frequency 1.2GHz 1.8GHz 1.5GHz No opp-supported-hw
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Limit
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------------------------------------------------------------
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936000000 1 1 1 1 0xf
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1104000000 1 1 1 1 0xf
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1200000000 1 1 1 1 0xf
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1416000000 0 1 1 1 0x7
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1488000000 0 1 1 1 0x7
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1800000000 0 1 0 1 0x5
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2208000000 0 0 0 1 0x1
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-----------------------------------------------------------
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++++++-
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1 file changed, 20 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -107,42 +107,56 @@
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};
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cpu_opp_table: opp-table-cpu {
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- compatible = "operating-points-v2";
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+ compatible = "operating-points-v2-kryo-cpu";
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opp-shared;
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+ nvmem-cells = <&cpu_speed_bin>;
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opp-936000000 {
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opp-hz = /bits/ 64 <936000000>;
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opp-microvolt = <725000>;
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+ opp-supported-hw = <0xf>;
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clock-latency-ns = <200000>;
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};
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opp-1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <787500>;
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+ opp-supported-hw = <0xf>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <862500>;
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+ opp-supported-hw = <0xf>;
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clock-latency-ns = <200000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <862500>;
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+ opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-1488000000 {
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opp-hz = /bits/ 64 <1488000000>;
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opp-microvolt = <925000>;
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+ opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <987500>;
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+ opp-supported-hw = <0x5>;
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clock-latency-ns = <200000>;
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};
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opp-2208000000 {
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opp-hz = /bits/ 64 <2208000000>;
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opp-microvolt = <1062500>;
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+ opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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};
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};
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@@ -234,6 +248,11 @@
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reg = <0x000a4000 0x5a1>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ cpu_speed_bin: cpu-speed-bin@15 {
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+ reg = <0x15 0x2>;
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+ bits = <7 2>;
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+ };
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};
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cryptobam: dma-controller@704000 {
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