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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
109 lines
3.2 KiB
Diff
109 lines
3.2 KiB
Diff
From 8737ec830ee32162858af7c1504169b05b313ab1 Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Tue, 30 Apr 2024 12:12:12 +0530
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Subject: [PATCH] clk: qcom: common: Add interconnect clocks support
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Unlike MSM platforms that manage NoC related clocks and scaling
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from RPM, IPQ SoCs dont involve RPM in managing NoC related
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clocks and there is no NoC scaling.
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However, there is a requirement to enable some NoC interface
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clocks for accessing the peripheral controllers present on
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these NoCs. Though exposing these as normal clocks would work,
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having a minimalistic interconnect driver to handle these clocks
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would make it consistent with other Qualcomm platforms resulting
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in common code paths. This is similar to msm8996-cbf's usage of
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icc-clk framework.
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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Link: https://lore.kernel.org/r/20240430064214.2030013-5-quic_varada@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/common.c | 35 ++++++++++++++++++++++++++++++++++-
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drivers/clk/qcom/common.h | 9 +++++++++
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2 files changed, 43 insertions(+), 1 deletion(-)
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--- a/drivers/clk/qcom/common.c
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+++ b/drivers/clk/qcom/common.c
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@@ -8,6 +8,7 @@
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#include <linux/regmap.h>
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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+#include <linux/interconnect-clk.h>
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#include <linux/reset-controller.h>
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#include <linux/of.h>
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@@ -250,6 +251,38 @@ static struct clk_hw *qcom_cc_clk_hw_get
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return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
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}
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+static int qcom_cc_icc_register(struct device *dev,
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+ const struct qcom_cc_desc *desc)
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+{
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+ struct icc_clk_data *icd;
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+ struct clk_hw *hws;
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+ int i;
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+
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+ if (!IS_ENABLED(CONFIG_INTERCONNECT_CLK))
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+ return 0;
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+
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+ if (!desc->icc_hws)
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+ return 0;
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+
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+ icd = devm_kcalloc(dev, desc->num_icc_hws, sizeof(*icd), GFP_KERNEL);
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+ if (!icd)
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+ return -ENOMEM;
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+
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+ for (i = 0; i < desc->num_icc_hws; i++) {
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+ icd[i].master_id = desc->icc_hws[i].master_id;
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+ icd[i].slave_id = desc->icc_hws[i].slave_id;
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+ hws = &desc->clks[desc->icc_hws[i].clk_id]->hw;
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+ icd[i].clk = devm_clk_hw_get_clk(dev, hws, "icc");
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+ if (!icd[i].clk)
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+ return dev_err_probe(dev, -ENOENT,
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+ "(%d) clock entry is null\n", i);
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+ icd[i].name = clk_hw_get_name(hws);
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+ }
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+
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+ return devm_icc_clk_register(dev, desc->icc_first_node_id,
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+ desc->num_icc_hws, icd);
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+}
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+
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int qcom_cc_really_probe(struct device *dev,
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const struct qcom_cc_desc *desc, struct regmap *regmap)
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{
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@@ -318,7 +351,7 @@ int qcom_cc_really_probe(struct device *
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if (ret)
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return ret;
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- return 0;
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+ return qcom_cc_icc_register(dev, desc);
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}
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EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
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--- a/drivers/clk/qcom/common.h
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+++ b/drivers/clk/qcom/common.h
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@@ -19,6 +19,12 @@ struct clk_hw;
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#define PLL_VOTE_FSM_ENA BIT(20)
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#define PLL_VOTE_FSM_RESET BIT(21)
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+struct qcom_icc_hws_data {
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+ int master_id;
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+ int slave_id;
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+ int clk_id;
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+};
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+
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struct qcom_cc_desc {
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const struct regmap_config *config;
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struct clk_regmap **clks;
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@@ -29,6 +35,9 @@ struct qcom_cc_desc {
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size_t num_gdscs;
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struct clk_hw **clk_hws;
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size_t num_clk_hws;
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+ struct qcom_icc_hws_data *icc_hws;
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+ size_t num_icc_hws;
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+ unsigned int icc_first_node_id;
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};
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/**
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