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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
130 lines
3.7 KiB
Diff
130 lines
3.7 KiB
Diff
From a8fe85d40ffe5ec0fd2f557932ffee902be35b38 Mon Sep 17 00:00:00 2001
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From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Date: Tue, 30 Apr 2024 23:07:44 -0500
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Subject: [PATCH] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
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The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by
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PCIe PHYs. Port the pipe clocks from the downstream 5.4 kernel.
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Link: https://lore.kernel.org/r/20240501040800.1542805-3-mr.nuke.me@gmail.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
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1 file changed, 76 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq9574.c
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+++ b/drivers/clk/qcom/gcc-ipq9574.c
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@@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_p
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},
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};
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+static struct clk_branch gcc_pcie0_pipe_clk = {
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+ .halt_reg = 0x28044,
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+ .halt_check = BRANCH_HALT_DELAY,
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+ .clkr = {
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+ .enable_reg = 0x28044,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(const struct clk_init_data) {
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+ .name = "gcc_pcie0_pipe_clk",
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+ .parent_hws = (const struct clk_hw *[]) {
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+ &pcie0_pipe_clk_src.clkr.hw
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
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.reg = 0x29064,
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.clkr = {
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@@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_p
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},
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};
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+static struct clk_branch gcc_pcie1_pipe_clk = {
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+ .halt_reg = 0x29044,
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+ .halt_check = BRANCH_HALT_DELAY,
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+ .clkr = {
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+ .enable_reg = 0x29044,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(const struct clk_init_data) {
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+ .name = "gcc_pcie1_pipe_clk",
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+ .parent_hws = (const struct clk_hw *[]) {
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+ &pcie1_pipe_clk_src.clkr.hw
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
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.reg = 0x2a064,
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.clkr = {
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@@ -1597,6 +1633,24 @@ static struct clk_regmap_phy_mux pcie2_p
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},
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};
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+static struct clk_branch gcc_pcie2_pipe_clk = {
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+ .halt_reg = 0x2a044,
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+ .halt_check = BRANCH_HALT_DELAY,
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+ .clkr = {
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+ .enable_reg = 0x2a044,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(const struct clk_init_data) {
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+ .name = "gcc_pcie2_pipe_clk",
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+ .parent_hws = (const struct clk_hw *[]) {
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+ &pcie2_pipe_clk_src.clkr.hw
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
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.reg = 0x2b064,
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.clkr = {
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@@ -1611,6 +1665,24 @@ static struct clk_regmap_phy_mux pcie3_p
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},
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};
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+static struct clk_branch gcc_pcie3_pipe_clk = {
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+ .halt_reg = 0x2b044,
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+ .halt_check = BRANCH_HALT_DELAY,
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+ .clkr = {
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+ .enable_reg = 0x2b044,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(const struct clk_init_data) {
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+ .name = "gcc_pcie3_pipe_clk",
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+ .parent_hws = (const struct clk_hw *[]) {
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+ &pcie3_pipe_clk_src.clkr.hw
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
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F(24000000, P_XO, 1, 0, 0),
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F(100000000, P_GPLL0, 8, 0, 0),
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@@ -4143,6 +4215,10 @@ static struct clk_regmap *gcc_ipq9574_cl
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[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
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[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
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[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
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+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
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+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
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+ [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
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+ [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
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};
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static const struct qcom_reset_map gcc_ipq9574_resets[] = {
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