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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
70 lines
2.4 KiB
Diff
70 lines
2.4 KiB
Diff
From 6dc140bcf2bed2bfd16f895dbe6c6da229cab2c6 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Mon, 10 Feb 2025 15:14:22 +0000
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Subject: [PATCH] PCI: brcmstb: set BCM7712/2712-specific AXI bridge handling
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behaviours
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These chips use a UBUS-AXI bridge component that has configurable
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timeout and error response handling.
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Suppress AXI error responses to CPU requests, otherwise these are fatal
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if they reach the ARM cluster, and set reasonably large timeouts for
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both Mem and Cfg requests.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 35 +++++++++++++++++++++++++++
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1 file changed, 35 insertions(+)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -209,6 +209,17 @@
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#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
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#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
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+/* BCM7712/2712-specific registers */
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+#define PCIE_MISC_UBUS_CTRL 0x40a4
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+#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK BIT(13)
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+#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK BIT(19)
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+
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+#define PCIE_MISC_UBUS_TIMEOUT 0x40a8
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+
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+#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT 0x405c
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+
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+#define PCIE_MISC_AXI_READ_ERROR_DATA 0x4170
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+
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/* Forward declarations */
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struct brcm_pcie;
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@@ -859,6 +870,30 @@ static int brcm_pcie_post_setup_bcm2712(
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tmp |= 0x12;
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writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15);
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+ /*
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+ * BCM7712/2712 uses a UBUS-AXI bridge.
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+ * Suppress AXI error responses and return 1s for read failures.
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+ */
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+ tmp = readl(pcie->base + PCIE_MISC_UBUS_CTRL);
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+ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK);
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+ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK);
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+ writel(tmp, pcie->base + PCIE_MISC_UBUS_CTRL);
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+ writel(0xffffffff, pcie->base + PCIE_MISC_AXI_READ_ERROR_DATA);
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+
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+ /*
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+ * Adjust timeouts. The UBUS timeout also affects Configuration Request
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+ * Retry responses, as the request will get terminated if
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+ * either timeout expires, so both have to be a large value
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+ * (in clocks of 750MHz).
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+ * Set UBUS timeout to 250ms, then set RC config retry timeout
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+ * to be ~240ms.
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+ *
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+ * If CRSSVE=1 this will stop the core from blocking on a Retry
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+ * response, but does require the device to be well-behaved...
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+ */
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+ writel(0xB2D0000, pcie->base + PCIE_MISC_UBUS_TIMEOUT);
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+ writel(0xABA0000, pcie->base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT);
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+
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return 0;
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}
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