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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
54 lines
1.9 KiB
Diff
54 lines
1.9 KiB
Diff
From 58397c19bbdf4e56582cb4149d254bbdde428167 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Mon, 9 Sep 2024 17:38:45 +0100
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Subject: [PATCH] drm/vc4: Drop panic priority for writeback connector
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As the writeback connector doesn't have the same realtime
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constraints of a live display, drop the panic priority for it.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_kms.c | 21 ++++++++++++++-------
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1 file changed, 14 insertions(+), 7 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_kms.c
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+++ b/drivers/gpu/drm/vc4/vc4_kms.c
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@@ -221,7 +221,7 @@ static void vc4_hvs_pv_muxing_commit(str
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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u32 dispctrl;
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- u32 dsp3_mux;
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+ u32 dsp3_mux_pri;
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if (!crtc_state->active)
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continue;
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@@ -238,15 +238,22 @@ static void vc4_hvs_pv_muxing_commit(str
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* enabled. In this case, FIFO 2 is directly accessed by the
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* TXP IP, and we need to disable the FIFO2 -> pixelvalve1
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* route.
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+ *
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+ * TXP can also run with a lower panic level than a live display,
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+ * as it doesn't have the same real-time constraint.
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*/
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- if (vc4_crtc->feeds_txp)
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- dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
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- else
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- dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
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+ if (vc4_crtc->feeds_txp) {
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+ dsp3_mux_pri = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
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+ dsp3_mux_pri |= VC4_SET_FIELD(0, SCALER_DISPCTRL_PANIC2);
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+ } else {
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+ dsp3_mux_pri = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
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+ dsp3_mux_pri |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
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+ }
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dispctrl = HVS_READ(SCALER_DISPCTRL) &
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- ~SCALER_DISPCTRL_DSP3_MUX_MASK;
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- HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
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+ ~(SCALER_DISPCTRL_DSP3_MUX_MASK |
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+ SCALER_DISPCTRL_PANIC2_MASK);
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+ HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux_pri);
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}
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}
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