mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
104 lines
3.6 KiB
Diff
104 lines
3.6 KiB
Diff
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
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+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -688,19 +688,20 @@ static void dwcmshc_rk3568_set_clock(str
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0x3 << 19; /* post-change delay */
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sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
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- if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
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- host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
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+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
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txclk_tapnum = priv->txclk_tapnum;
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- if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
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+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
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txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
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- extra = DLL_CMDOUT_SRC_CLK_NEG |
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- DLL_CMDOUT_EN_SRC_CLK_NEG |
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- DWCMSHC_EMMC_DLL_DLYENA |
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- DLL_CMDOUT_TAPNUM_90_DEGREES |
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- DLL_CMDOUT_TAPNUM_FROM_SW;
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- sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
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+ if (priv->devtype != DWCMSHC_RK3568) {
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+ extra = DLL_CMDOUT_SRC_CLK_NEG |
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+ DLL_CMDOUT_EN_SRC_CLK_NEG |
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+ DWCMSHC_EMMC_DLL_DLYENA |
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+ DLL_CMDOUT_TAPNUM_90_DEGREES |
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+ DLL_CMDOUT_TAPNUM_FROM_SW;
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+ sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
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+ }
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}
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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@@ -741,10 +742,10 @@ static int dwcmshc_rk35xx_init(struct de
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if (!priv)
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return -ENOMEM;
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- if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc"))
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- priv->devtype = DWCMSHC_RK3588;
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- else
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+ if (of_device_is_compatible(dev->of_node, "rockchip,rk3568-dwcmshc"))
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priv->devtype = DWCMSHC_RK3568;
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+ else
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+ priv->devtype = DWCMSHC_RK3588;
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priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
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if (IS_ERR(priv->reset)) {
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@@ -1156,6 +1157,16 @@ static const struct sdhci_ops sdhci_dwcm
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.irq = dwcmshc_cqe_irq_handler,
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};
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+static const struct sdhci_ops sdhci_dwcmshc_rk3528_ops = {
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+ .set_clock = dwcmshc_rk3568_set_clock,
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+ .set_bus_width = sdhci_set_bus_width,
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+ .set_uhs_signaling = dwcmshc_set_uhs_signaling,
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+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
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+ .reset = rk35xx_sdhci_reset,
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+ .adma_write_desc = dwcmshc_adma_write_desc,
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+ .irq = dwcmshc_cqe_irq_handler,
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+};
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+
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static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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@@ -1218,6 +1229,18 @@ static const struct dwcmshc_pltfm_data s
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.postinit = dwcmshc_rk35xx_postinit,
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};
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+static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk3528_pdata = {
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+ .pdata = {
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+ .ops = &sdhci_dwcmshc_rk3528_ops,
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+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
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+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
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+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
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+ },
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+ .init = dwcmshc_rk35xx_init,
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+ .postinit = dwcmshc_rk35xx_postinit,
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+};
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+
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static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = {
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.pdata = {
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.ops = &sdhci_dwcmshc_th1520_ops,
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@@ -1320,6 +1343,10 @@ static const struct of_device_id sdhci_d
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.compatible = "rockchip,rk3568-dwcmshc",
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.data = &sdhci_dwcmshc_rk35xx_pdata,
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},
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+ {
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+ .compatible = "rockchip,rk3528-dwcmshc",
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+ .data = &sdhci_dwcmshc_rk3528_pdata,
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+ },
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{
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.compatible = "snps,dwcmshc-sdhci",
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.data = &sdhci_dwcmshc_pdata,
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--- a/drivers/pci/controller/dwc/Makefile
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+++ b/drivers/pci/controller/dwc/Makefile
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@@ -18,6 +18,7 @@ obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_ROCKCHIP_DW) += pcie-dw-rockchip.o
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+obj-$(CONFIG_PCIE_ROCKCHIP_DW) += pcie-dw-rkvendor.o
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obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
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obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o
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obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
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