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https://github.com/coolsnowwolf/lede.git
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127 lines
3.9 KiB
Diff
127 lines
3.9 KiB
Diff
From 7b20271bc8c2982ab1e7bcfcf896ca5320b16a6f Mon Sep 17 00:00:00 2001
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From: Kathiravan T <quic_kathirav@quicinc.com>
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Date: Fri, 17 Feb 2023 14:03:06 +0530
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Subject: [PATCH 39/41] clk: qcom: apss-ipq-pll: add support for IPQ5332
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IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same.
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To configure the stromer plus PLL separate API
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(clock_stromer_pll_configure) to be used. To achieve this, introduce the
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new member pll_type in device data structure and call the appropriate
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function based on this.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230217083308.12017-4-quic_kathirav@quicinc.com
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---
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drivers/clk/qcom/apss-ipq-pll.c | 59 ++++++++++++++++++++++++++++++++-
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1 file changed, 58 insertions(+), 1 deletion(-)
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--- a/drivers/clk/qcom/apss-ipq-pll.c
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+++ b/drivers/clk/qcom/apss-ipq-pll.c
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@@ -24,6 +24,18 @@ static const u8 ipq_pll_offsets[][PLL_OF
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[PLL_OFF_TEST_CTL] = 0x30,
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[PLL_OFF_TEST_CTL_U] = 0x34,
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},
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+
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+ [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
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+ [PLL_OFF_L_VAL] = 0x08,
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+ [PLL_OFF_ALPHA_VAL] = 0x10,
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+ [PLL_OFF_ALPHA_VAL_U] = 0x14,
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+ [PLL_OFF_USER_CTL] = 0x18,
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+ [PLL_OFF_USER_CTL_U] = 0x1c,
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+ [PLL_OFF_CONFIG_CTL] = 0x20,
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+ [PLL_OFF_STATUS] = 0x28,
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+ [PLL_OFF_TEST_CTL] = 0x30,
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+ [PLL_OFF_TEST_CTL_U] = 0x34,
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+ },
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};
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static struct clk_alpha_pll ipq_pll_huayra = {
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@@ -44,6 +56,38 @@ static struct clk_alpha_pll ipq_pll_huay
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},
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};
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+static struct clk_alpha_pll ipq_pll_stromer_plus = {
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+ .offset = 0x0,
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+ .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
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+ .flags = SUPPORTS_DYNAMIC_UPDATE,
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+ .clkr = {
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+ .enable_reg = 0x0,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "a53pll",
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+ .parent_data = &(const struct clk_parent_data) {
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+ .fw_name = "xo",
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_alpha_pll_stromer_ops,
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+ },
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+ },
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+};
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+
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+static const struct alpha_pll_config ipq5332_pll_config = {
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+ .l = 0x3e,
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+ .config_ctl_val = 0x4001075b,
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+ .config_ctl_hi_val = 0x304,
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+ .main_output_mask = BIT(0),
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+ .aux_output_mask = BIT(1),
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+ .early_output_mask = BIT(3),
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+ .alpha_en_mask = BIT(24),
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+ .status_val = 0x3,
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+ .status_mask = GENMASK(10, 8),
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+ .lock_det = BIT(2),
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+ .test_ctl_hi_val = 0x00400003,
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+};
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+
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static const struct alpha_pll_config ipq6018_pll_config = {
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.l = 0x37,
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.config_ctl_val = 0x240d4828,
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@@ -81,16 +125,25 @@ static const struct alpha_pll_config ipq
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};
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struct apss_pll_data {
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+ int pll_type;
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struct clk_alpha_pll *pll;
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const struct alpha_pll_config *pll_config;
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};
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+static struct apss_pll_data ipq5332_pll_data = {
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+ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
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+ .pll = &ipq_pll_stromer_plus,
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+ .pll_config = &ipq5332_pll_config,
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+};
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+
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static struct apss_pll_data ipq8074_pll_data = {
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+ .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
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.pll = &ipq_pll_huayra,
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.pll_config = &ipq8074_pll_config,
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};
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static struct apss_pll_data ipq6018_pll_data = {
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+ .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
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.pll = &ipq_pll_huayra,
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.pll_config = &ipq6018_pll_config,
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};
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@@ -129,7 +182,10 @@ static int apss_ipq_pll_probe(struct pla
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if (!data)
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return -ENODEV;
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- clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
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+ if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
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+ clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
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+ else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
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+ clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
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ret = devm_clk_register_regmap(dev, &data->pll->clkr);
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if (ret)
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@@ -140,6 +196,7 @@ static int apss_ipq_pll_probe(struct pla
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}
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static const struct of_device_id apss_ipq_pll_match_table[] = {
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+ { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
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{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
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{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
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{ .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
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