mirror of
https://github.com/coolsnowwolf/lede.git
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58 lines
1.7 KiB
Diff
58 lines
1.7 KiB
Diff
From f0869d5304a548b18bd0402ed2ebe6e6fa66ec04 Mon Sep 17 00:00:00 2001
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From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Date: Thu, 14 Sep 2023 12:29:54 +0530
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Subject: [PATCH 32/41] clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag
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from GPLL clocks
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GPLL clock rates are fixed and shouldn't be scaled based on the request
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from dependent clocks. Doing so will result in the unexpected behaviour.
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So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.
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----
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Changes in V2:
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- No changes
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Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
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Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-4-c8ceb1a37680@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/gcc-ipq9574.c | 4 ----
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1 file changed, 4 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq9574.c
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+++ b/drivers/clk/qcom/gcc-ipq9574.c
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@@ -87,7 +87,6 @@ static struct clk_fixed_factor gpll0_out
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&gpll0_main.clkr.hw
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},
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.num_parents = 1,
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- .flags = CLK_SET_RATE_PARENT,
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.ops = &clk_fixed_factor_ops,
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},
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};
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@@ -102,7 +101,6 @@ static struct clk_alpha_pll_postdiv gpll
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&gpll0_main.clkr.hw
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},
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.num_parents = 1,
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- .flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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},
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};
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@@ -132,7 +130,6 @@ static struct clk_alpha_pll_postdiv gpll
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&gpll4_main.clkr.hw
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},
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.num_parents = 1,
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- .flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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},
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};
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@@ -162,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll
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&gpll2_main.clkr.hw
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},
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.num_parents = 1,
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- .flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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},
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};
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