mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
159 lines
4.1 KiB
Diff
159 lines
4.1 KiB
Diff
From e218ade7d728582bce795f6cce6fff39c4107dd5 Mon Sep 17 00:00:00 2001
|
|
From: Devi Priya <quic_devipriy@quicinc.com>
|
|
Date: Wed, 10 May 2023 16:13:59 +0530
|
|
Subject: [PATCH 16/41] arm64: dts: qcom: ipq9574: add support for RDP418
|
|
variant
|
|
|
|
Add the initial device tree support for the Reference Design Platform (RDP)
|
|
418 based on IPQ9574 family of SoCs. This patch adds support for Console
|
|
UART, SPI NOR, eMMC and SMPA1 regulator node.
|
|
|
|
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
|
|
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
|
|
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
|
|
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
Link: https://lore.kernel.org/r/20230510104359.16678-3-quic_devipriy@quicinc.com
|
|
---
|
|
arch/arm64/boot/dts/qcom/Makefile | 1 +
|
|
arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 124 ++++++++++++++++++++
|
|
2 files changed, 125 insertions(+)
|
|
create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/Makefile
|
|
+++ b/arch/arm64/boot/dts/qcom/Makefile
|
|
@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-
|
|
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
|
|
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
|
|
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
|
|
+dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb
|
|
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
|
|
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
|
|
dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
|
|
@@ -0,0 +1,124 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
+/*
|
|
+ * IPQ9574 RDP418 board device tree source
|
|
+ *
|
|
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
|
|
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "ipq9574.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
|
|
+ compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &blsp1_uart2;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+};
|
|
+
|
|
+&blsp1_spi0 {
|
|
+ pinctrl-0 = <&spi_0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+
|
|
+ flash@0 {
|
|
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ spi-max-frequency = <50000000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&blsp1_uart2 {
|
|
+ pinctrl-0 = <&uart2_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rpm_requests {
|
|
+ regulators {
|
|
+ compatible = "qcom,rpm-mp5496-regulators";
|
|
+
|
|
+ ipq9574_s1: s1 {
|
|
+ /*
|
|
+ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
|
|
+ * During regulator registration, kernel not knowing the initial voltage,
|
|
+ * considers it as zero and brings up the regulators with minimum supported voltage.
|
|
+ * Update the regulator-min-microvolt with SVS voltage of 725mV so that
|
|
+ * the regulators are brought up with 725mV which is sufficient for all the
|
|
+ * corner parts to operate at 800MHz
|
|
+ */
|
|
+ regulator-min-microvolt = <725000>;
|
|
+ regulator-max-microvolt = <1075000>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdhc_1 {
|
|
+ pinctrl-0 = <&sdc_default_state>;
|
|
+ pinctrl-names = "default";
|
|
+ mmc-ddr-1_8v;
|
|
+ mmc-hs200-1_8v;
|
|
+ mmc-hs400-1_8v;
|
|
+ mmc-hs400-enhanced-strobe;
|
|
+ max-frequency = <384000000>;
|
|
+ bus-width = <8>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sleep_clk {
|
|
+ clock-frequency = <32000>;
|
|
+};
|
|
+
|
|
+&tlmm {
|
|
+ sdc_default_state: sdc-default-state {
|
|
+ clk-pins {
|
|
+ pins = "gpio5";
|
|
+ function = "sdc_clk";
|
|
+ drive-strength = <8>;
|
|
+ bias-disable;
|
|
+ };
|
|
+
|
|
+ cmd-pins {
|
|
+ pins = "gpio4";
|
|
+ function = "sdc_cmd";
|
|
+ drive-strength = <8>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ data-pins {
|
|
+ pins = "gpio0", "gpio1", "gpio2",
|
|
+ "gpio3", "gpio6", "gpio7",
|
|
+ "gpio8", "gpio9";
|
|
+ function = "sdc_data";
|
|
+ drive-strength = <8>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ rclk-pins {
|
|
+ pins = "gpio10";
|
|
+ function = "sdc_rclk";
|
|
+ drive-strength = <8>;
|
|
+ bias-pull-down;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi_0_pins: spi-0-state {
|
|
+ pins = "gpio11", "gpio12", "gpio13", "gpio14";
|
|
+ function = "blsp0_spi";
|
|
+ drive-strength = <8>;
|
|
+ bias-disable;
|
|
+ };
|
|
+};
|
|
+
|
|
+&xo_board_clk {
|
|
+ clock-frequency = <24000000>;
|
|
+};
|