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204 lines
4.6 KiB
Diff
204 lines
4.6 KiB
Diff
From 89978464908147356b67ee57dd07482dc7ffe332 Mon Sep 17 00:00:00 2001
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From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Tue, 25 Apr 2023 14:10:10 +0530
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Subject: [PATCH 13/41] arm64: dts: qcom: ipq9574: rename al02-c7 dts to rdp433
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Rename the dts after Reference Design Platform(RDP) to adopt
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standard naming convention.
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Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230425084010.15581-7-quic_devipriy@quicinc.com
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---
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arch/arm64/boot/dts/qcom/Makefile | 2 +-
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.../boot/dts/qcom/{ipq9574-al02-c7.dts => ipq9574-rdp433.dts} | 2 +-
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2 files changed, 2 insertions(+), 2 deletions(-)
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rename arch/arm64/boot/dts/qcom/{ipq9574-al02-c7.dts => ipq9574-rdp433.dts} (97%)
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--- a/arch/arm64/boot/dts/qcom/Makefile
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+++ b/arch/arm64/boot/dts/qcom/Makefile
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@@ -7,7 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
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-dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb
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+dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb
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--- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
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+++ /dev/null
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@@ -1,84 +0,0 @@
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-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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-/*
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- * IPQ9574 AL02-C7 board device tree source
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- *
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- * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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- */
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-
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-/dts-v1/;
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-
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-#include "ipq9574.dtsi"
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-
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-/ {
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- model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
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- compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
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-
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- aliases {
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- serial0 = &blsp1_uart2;
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- };
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-
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- chosen {
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- stdout-path = "serial0:115200n8";
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- };
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-};
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-
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-&blsp1_uart2 {
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- pinctrl-0 = <&uart2_pins>;
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- pinctrl-names = "default";
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- status = "okay";
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-};
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-
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-&sdhc_1 {
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- pinctrl-0 = <&sdc_default_state>;
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- pinctrl-names = "default";
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- mmc-ddr-1_8v;
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- mmc-hs200-1_8v;
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- mmc-hs400-1_8v;
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- mmc-hs400-enhanced-strobe;
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- max-frequency = <384000000>;
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- bus-width = <8>;
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- status = "okay";
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-};
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-
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-&sleep_clk {
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- clock-frequency = <32000>;
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-};
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-
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-&tlmm {
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- sdc_default_state: sdc-default-state {
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- clk-pins {
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- pins = "gpio5";
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- function = "sdc_clk";
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- drive-strength = <8>;
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- bias-disable;
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- };
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-
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- cmd-pins {
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- pins = "gpio4";
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- function = "sdc_cmd";
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- drive-strength = <8>;
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- bias-pull-up;
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- };
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-
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- data-pins {
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- pins = "gpio0", "gpio1", "gpio2",
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- "gpio3", "gpio6", "gpio7",
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- "gpio8", "gpio9";
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- function = "sdc_data";
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- drive-strength = <8>;
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- bias-pull-up;
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- };
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-
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- rclk-pins {
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- pins = "gpio10";
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- function = "sdc_rclk";
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- drive-strength = <8>;
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- bias-pull-down;
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- };
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- };
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-};
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-
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-&xo_board_clk {
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- clock-frequency = <24000000>;
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-};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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@@ -0,0 +1,84 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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+/*
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+ * IPQ9574 RDP433 board device tree source
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+ *
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+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+/dts-v1/;
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+
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+#include "ipq9574.dtsi"
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+
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+/ {
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+ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
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+ compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
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+
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+ aliases {
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+ serial0 = &blsp1_uart2;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+};
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+
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+&blsp1_uart2 {
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+ pinctrl-0 = <&uart2_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&sdhc_1 {
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+ pinctrl-0 = <&sdc_default_state>;
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+ pinctrl-names = "default";
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+ mmc-ddr-1_8v;
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+ mmc-hs200-1_8v;
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+ mmc-hs400-1_8v;
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+ mmc-hs400-enhanced-strobe;
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+ max-frequency = <384000000>;
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+ bus-width = <8>;
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+ status = "okay";
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+};
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+
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+&sleep_clk {
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+ clock-frequency = <32000>;
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+};
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+
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+&tlmm {
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+ sdc_default_state: sdc-default-state {
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+ clk-pins {
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+ pins = "gpio5";
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+ function = "sdc_clk";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ cmd-pins {
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+ pins = "gpio4";
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+ function = "sdc_cmd";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+
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+ data-pins {
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+ pins = "gpio0", "gpio1", "gpio2",
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+ "gpio3", "gpio6", "gpio7",
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+ "gpio8", "gpio9";
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+ function = "sdc_data";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+
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+ rclk-pins {
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+ pins = "gpio10";
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+ function = "sdc_rclk";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+ };
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+};
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+
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+&xo_board_clk {
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+ clock-frequency = <24000000>;
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+};
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