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https://github.com/coolsnowwolf/lede.git
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223 lines
7.1 KiB
Diff
223 lines
7.1 KiB
Diff
From 5bd9fcb9c152a9ed0c9bb22e403d4df359faad7b Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Tue, 7 Mar 2023 11:52:24 +0530
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Subject: [PATCH 03/41] clk: qcom: clk-alpha-pll: Add support for Stromer PLLs
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Add programming sequence support for managing the Stromer
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PLLs.
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Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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Co-developed-by: Sricharan R <quic_srichara@quicinc.com>
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Signed-off-by: Sricharan R <quic_srichara@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230307062232.4889-2-quic_kathirav@quicinc.com
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---
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drivers/clk/qcom/clk-alpha-pll.c | 128 ++++++++++++++++++++++++++++++-
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drivers/clk/qcom/clk-alpha-pll.h | 13 +++-
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2 files changed, 139 insertions(+), 2 deletions(-)
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--- a/drivers/clk/qcom/clk-alpha-pll.c
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+++ b/drivers/clk/qcom/clk-alpha-pll.c
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@@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
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- * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
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+ * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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@@ -188,6 +188,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MA
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[PLL_OFF_CONFIG_CTL] = 0x1C,
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[PLL_OFF_STATUS] = 0x20,
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},
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+ [CLK_ALPHA_PLL_TYPE_STROMER] = {
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+ [PLL_OFF_L_VAL] = 0x08,
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+ [PLL_OFF_ALPHA_VAL] = 0x10,
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+ [PLL_OFF_ALPHA_VAL_U] = 0x14,
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+ [PLL_OFF_USER_CTL] = 0x18,
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+ [PLL_OFF_USER_CTL_U] = 0x1c,
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+ [PLL_OFF_CONFIG_CTL] = 0x20,
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+ [PLL_OFF_CONFIG_CTL_U] = 0xff,
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+ [PLL_OFF_TEST_CTL] = 0x30,
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+ [PLL_OFF_TEST_CTL_U] = 0x34,
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+ [PLL_OFF_STATUS] = 0x28,
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+ },
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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@@ -199,6 +211,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define ALPHA_BITWIDTH 32U
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#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
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+#define ALPHA_PLL_STATUS_REG_SHIFT 8
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+
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#define PLL_HUAYRA_M_WIDTH 8
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#define PLL_HUAYRA_M_SHIFT 8
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#define PLL_HUAYRA_M_MASK 0xff
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@@ -2360,3 +2374,115 @@ const struct clk_ops clk_alpha_pll_rivia
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.round_rate = clk_rivian_evo_pll_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
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+
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+void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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+ const struct alpha_pll_config *config)
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+{
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+ u32 val, val_u, mask, mask_u;
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+
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+ regmap_write(regmap, PLL_L_VAL(pll), config->l);
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+ regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
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+ regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
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+
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+ if (pll_has_64bit_config(pll))
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+ regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
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+ config->config_ctl_hi_val);
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+
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+ if (pll_alpha_width(pll) > 32)
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+ regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
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+
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+ val = config->main_output_mask;
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+ val |= config->aux_output_mask;
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+ val |= config->aux2_output_mask;
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+ val |= config->early_output_mask;
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+ val |= config->pre_div_val;
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+ val |= config->post_div_val;
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+ val |= config->vco_val;
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+ val |= config->alpha_en_mask;
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+ val |= config->alpha_mode_mask;
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+
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+ mask = config->main_output_mask;
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+ mask |= config->aux_output_mask;
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+ mask |= config->aux2_output_mask;
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+ mask |= config->early_output_mask;
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+ mask |= config->pre_div_mask;
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+ mask |= config->post_div_mask;
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+ mask |= config->vco_mask;
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+ mask |= config->alpha_en_mask;
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+ mask |= config->alpha_mode_mask;
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+
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+ regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
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+
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+ /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
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+ val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
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+ val_u |= config->lock_det;
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+
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+ mask_u = config->status_mask;
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+ mask_u |= config->lock_det;
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+
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+ regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
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+ regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
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+ regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
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+
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+ if (pll->flags & SUPPORTS_FSM_MODE)
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+ qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
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+}
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+EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
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+
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+static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
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+ struct clk_rate_request *req)
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+{
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+ u32 l;
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+ u64 a;
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+
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+ req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
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+ &l, &a, ALPHA_REG_BITWIDTH);
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+
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+ return 0;
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+}
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+
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+static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long prate)
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+{
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+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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+ int ret;
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+ u32 l;
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+ u64 a;
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+
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+ rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
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+
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+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
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+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
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+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
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+ a >> ALPHA_BITWIDTH);
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+
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+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
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+ PLL_ALPHA_EN, PLL_ALPHA_EN);
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+
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+ if (!clk_hw_is_enabled(hw))
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+ return 0;
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+
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+ /*
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+ * Stromer PLL supports Dynamic programming.
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+ * It allows the PLL frequency to be changed on-the-fly without first
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+ * execution of a shutdown procedure followed by a bring up procedure.
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+ */
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+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
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+ PLL_UPDATE);
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+
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+ ret = wait_for_pll_update(pll);
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+ if (ret)
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+ return ret;
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+
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+ return wait_for_pll_enable_lock(pll);
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+}
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+
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+const struct clk_ops clk_alpha_pll_stromer_ops = {
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+ .enable = clk_alpha_pll_enable,
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+ .disable = clk_alpha_pll_disable,
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+ .is_enabled = clk_alpha_pll_is_enabled,
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+ .recalc_rate = clk_alpha_pll_recalc_rate,
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+ .determine_rate = clk_alpha_pll_stromer_determine_rate,
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+ .set_rate = clk_alpha_pll_stromer_set_rate,
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+};
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+EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
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--- a/drivers/clk/qcom/clk-alpha-pll.h
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+++ b/drivers/clk/qcom/clk-alpha-pll.h
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@@ -1,5 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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-/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
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+/*
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+ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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#ifndef __QCOM_CLK_ALPHA_PLL_H__
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#define __QCOM_CLK_ALPHA_PLL_H__
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@@ -21,6 +25,7 @@ enum {
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CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
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CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
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CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
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+ CLK_ALPHA_PLL_TYPE_STROMER,
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CLK_ALPHA_PLL_TYPE_MAX,
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};
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@@ -128,6 +133,9 @@ struct alpha_pll_config {
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u32 post_div_mask;
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u32 vco_val;
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u32 vco_mask;
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+ u32 status_val;
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+ u32 status_mask;
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+ u32 lock_det;
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};
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extern const struct clk_ops clk_alpha_pll_ops;
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@@ -136,6 +144,7 @@ extern const struct clk_ops clk_alpha_pl
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extern const struct clk_ops clk_alpha_pll_postdiv_ops;
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extern const struct clk_ops clk_alpha_pll_huayra_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
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+extern const struct clk_ops clk_alpha_pll_stromer_ops;
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extern const struct clk_ops clk_alpha_pll_fabia_ops;
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extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
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@@ -184,5 +193,7 @@ void clk_lucid_evo_pll_configure(struct
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const struct alpha_pll_config *config);
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void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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+void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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+ const struct alpha_pll_config *config);
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#endif
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