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123 lines
3.9 KiB
Diff
123 lines
3.9 KiB
Diff
From 19cd9f8fc024ba70659411f00fd8c4f4a3814647 Mon Sep 17 00:00:00 2001
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From: Kathiravan T <quic_kathirav@quicinc.com>
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Date: Fri, 17 Feb 2023 14:03:04 +0530
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Subject: [PATCH 02/41] clk: qcom: apss-ipq-pll: refactor the driver to
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accommodate different PLL types
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APSS PLL found on the IPQ8074 and IPQ6018 are of type Huayra PLL. But,
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IPQ5332 APSS PLL is of type Stromer Plus. To accommodate both these PLLs,
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refactor the driver to take the clk_alpha_pll, alpha_pll_config via driver
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data.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230217083308.12017-2-quic_kathirav@quicinc.com
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---
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drivers/clk/qcom/apss-ipq-pll.c | 60 ++++++++++++++++++++++-----------
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1 file changed, 41 insertions(+), 19 deletions(-)
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--- a/drivers/clk/qcom/apss-ipq-pll.c
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+++ b/drivers/clk/qcom/apss-ipq-pll.c
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@@ -8,20 +8,27 @@
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#include "clk-alpha-pll.h"
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-static const u8 ipq_pll_offsets[] = {
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- [PLL_OFF_L_VAL] = 0x08,
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- [PLL_OFF_ALPHA_VAL] = 0x10,
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- [PLL_OFF_USER_CTL] = 0x18,
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- [PLL_OFF_CONFIG_CTL] = 0x20,
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- [PLL_OFF_CONFIG_CTL_U] = 0x24,
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- [PLL_OFF_STATUS] = 0x28,
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- [PLL_OFF_TEST_CTL] = 0x30,
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- [PLL_OFF_TEST_CTL_U] = 0x34,
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+/*
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+ * Even though APSS PLL type is of existing one (like Huayra), its offsets
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+ * are different from the one mentioned in the clk-alpha-pll.c, since the
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+ * PLL is specific to APSS, so lets the define the same.
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+ */
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+static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
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+ [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
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+ [PLL_OFF_L_VAL] = 0x08,
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+ [PLL_OFF_ALPHA_VAL] = 0x10,
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+ [PLL_OFF_USER_CTL] = 0x18,
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+ [PLL_OFF_CONFIG_CTL] = 0x20,
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+ [PLL_OFF_CONFIG_CTL_U] = 0x24,
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+ [PLL_OFF_STATUS] = 0x28,
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+ [PLL_OFF_TEST_CTL] = 0x30,
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+ [PLL_OFF_TEST_CTL_U] = 0x34,
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+ },
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};
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-static struct clk_alpha_pll ipq_pll = {
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+static struct clk_alpha_pll ipq_pll_huayra = {
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.offset = 0x0,
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- .regs = ipq_pll_offsets,
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+ .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA],
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.clkr = {
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.enable_reg = 0x0,
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@@ -61,6 +68,21 @@ static const struct alpha_pll_config ipq
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.test_ctl_hi_val = 0x4000,
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};
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+struct apss_pll_data {
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+ struct clk_alpha_pll *pll;
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+ const struct alpha_pll_config *pll_config;
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+};
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+
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+static struct apss_pll_data ipq8074_pll_data = {
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+ .pll = &ipq_pll_huayra,
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+ .pll_config = &ipq8074_pll_config,
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+};
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+
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+static struct apss_pll_data ipq6018_pll_data = {
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+ .pll = &ipq_pll_huayra,
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+ .pll_config = &ipq6018_pll_config,
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+};
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+
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static const struct regmap_config ipq_pll_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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@@ -71,7 +93,7 @@ static const struct regmap_config ipq_pl
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static int apss_ipq_pll_probe(struct platform_device *pdev)
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{
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- const struct alpha_pll_config *ipq_pll_config;
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+ const struct apss_pll_data *data;
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struct device *dev = &pdev->dev;
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struct regmap *regmap;
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void __iomem *base;
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@@ -85,23 +107,23 @@ static int apss_ipq_pll_probe(struct pla
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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- ipq_pll_config = of_device_get_match_data(&pdev->dev);
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- if (!ipq_pll_config)
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+ data = of_device_get_match_data(&pdev->dev);
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+ if (!data)
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return -ENODEV;
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- clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config);
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+ clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
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- ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
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+ ret = devm_clk_register_regmap(dev, &data->pll->clkr);
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if (ret)
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return ret;
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
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- &ipq_pll.clkr.hw);
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+ &data->pll->clkr.hw);
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}
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static const struct of_device_id apss_ipq_pll_match_table[] = {
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- { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
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- { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
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+ { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
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+ { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
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{ }
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};
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MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
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