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48 lines
1.4 KiB
Diff
48 lines
1.4 KiB
Diff
From b5a258e564a70e0fed38ada2a03e99688fc38e85 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Mon, 6 Jun 2022 23:46:28 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq6018: add SDHCI controller node
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Add the required DT node for SDCC v5 SDHCI controller.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -257,6 +257,32 @@
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reg = <0x0 0x01937000 0x0 0x21000>;
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};
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+ sdhci: mmc@780400 {
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+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
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+ reg = <0x0 0x07804000 0x0 0x1000>,
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+ <0x0 0x07805000 0x0 0x1000>,
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+ <0x0 0x07808000 0x0 0x2000>;
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+ reg-names = "hc", "cqhci", "ice";
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+
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hc_irq", "pwr_irq";
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+
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+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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+ <&gcc GCC_SDCC1_APPS_CLK>,
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+ <&xo>,
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+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
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+ clock-names = "iface", "core", "xo", "ice";
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+ resets = <&gcc GCC_SDCC1_BCR>;
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+ max-frequency = <192000000>;
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+ mmc-ddr-1_8v;
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+ mmc-hs200-1_8v;
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+ sd-uhs-sdr104;
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+ bus-width = <8>;
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+ vqmmc-supply = <&ipq6018_l2>;
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+ status = "disabled";
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+ };
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+
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x0 0x07884000 0x0 0x2b000>;
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