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41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
From 3d44861d006b18649306cbade242c865e9068b6e Mon Sep 17 00:00:00 2001
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From: Kathiravan T <quic_kathirav@quicinc.com>
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Date: Tue, 8 Feb 2022 21:05:25 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq6018: enable the GICv2m support
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GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension,
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which supports upto 32 MSI interrupts. Lets add support for the same.
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@quicinc.com
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -373,6 +373,8 @@
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
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@@ -380,6 +382,13 @@
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<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
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<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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+ ranges = <0 0 0 0xb00a000 0 0xffd>;
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+
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+ v2m@0 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x0 0x0 0x0 0xffd>;
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+ };
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};
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pcie_phy: phy@84000 {
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