mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
99 lines
2.4 KiB
Diff
99 lines
2.4 KiB
Diff
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
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@@ -8,6 +8,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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+#include "rk3328-dram-default-timing.dtsi"
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#include "rk3328.dtsi"
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/ {
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@@ -89,6 +90,71 @@
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regulator-boot-on;
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vin-supply = <&vcc_sys>;
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};
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+
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+ dmc: dmc {
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+ compatible = "rockchip,rk3328-dmc";
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+ devfreq-events = <&dfi>;
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+ center-supply = <&vdd_log>;
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+ clocks = <&cru SCLK_DDRCLK>;
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+ clock-names = "dmc_clk";
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+ operating-points-v2 = <&dmc_opp_table>;
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+ ddr_timing = <&ddr_timing>;
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+ upthreshold = <40>;
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+ downdifferential = <20>;
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+ auto-min-freq = <786000>;
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+ auto-freq-en = <0>;
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+ #cooling-cells = <2>;
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+
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+ ddr_power_model: ddr_power_model {
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+ compatible = "ddr_power_model";
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+ dynamic-power-coefficient = <120>;
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+ static-power-coefficient = <200>;
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+ ts = <32000 4700 (-80) 2>;
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+ thermal-zone = "soc-thermal";
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+ };
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+ };
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+
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+ dmc_opp_table: dmc-opp-table {
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+ compatible = "operating-points-v2";
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+
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+ rockchip,leakage-voltage-sel = <
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+ 1 10 0
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+ 11 254 1
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+ >;
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+ nvmem-cells = <&logic_leakage>;
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+ nvmem-cell-names = "ddr_leakage";
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+
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+ opp-786000000 {
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+ opp-hz = /bits/ 64 <786000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-798000000 {
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+ opp-hz = /bits/ 64 <798000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-840000000 {
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+ opp-hz = /bits/ 64 <840000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-924000000 {
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+ opp-hz = /bits/ 64 <924000000>;
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+ opp-microvolt = <1100000>;
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+ opp-microvolt-L0 = <1100000>;
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+ opp-microvolt-L1 = <1075000>;
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+ };
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+ opp-1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1175000>;
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+ opp-microvolt-L0 = <1175000>;
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+ opp-microvolt-L1 = <1150000>;
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+ };
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+ };
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};
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&cpu0 {
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--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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@@ -14,6 +14,13 @@
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compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
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};
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+&dmc_opp_table {
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+ /delete-node/ opp-798000000;
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+ /delete-node/ opp-840000000;
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+ /delete-node/ opp-924000000;
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+ /delete-node/ opp-1056000000;
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+};
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+
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&gmac2io {
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phy-handle = <&yt8531c>;
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tx_delay = <0x19>;
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