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cd264e8258
adjusted: target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch https://kernel.source.codeaurora.cn/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/clk/qcom/gcc-ipq8074.c?h=v5.10.137&id=b28ebe7d2f10e5ca574be3d4188a744674e8e0d5 https://kernel.source.codeaurora.cn/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/clk/qcom/gcc-ipq8074.c?h=v5.10.137&id=e2330494f0f8f168ae5bd17df01cb61363593c46 removed: target/linux/ipq807x/patches-5.10/128-qcom-clk-ipq8074-fix-port-6-clock-issue-for-1G.patch target/linux/ipq807x/patches-5.10/129-clk-qcom-ipq8074-Add-NSS-PORT-clocks-frequencies.patch target/linux/ipq807x/patches-5.10/130-clk-qcom-ipq8074-change-freq-table-for-port5_tx_clk_.patch https://kernel.source.codeaurora.cn/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/clk/qcom/gcc-ipq8074.c?h=v5.10.137&id=b83af7b4ec1d1c54de7d7115c9e0b4c3d60fdc47 Signed-off-by: José Hwong <josehwong@hotmail.com> Signed-off-by: José Hwong <josehwong@hotmail.com>
30 lines
1.2 KiB
Diff
30 lines
1.2 KiB
Diff
From a801cc475f0d1fdf29d7b6b56d64df090bf83f8d Mon Sep 17 00:00:00 2001
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From: Praveenkumar I <ipkumar@codeaurora.org>
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Date: Fri, 3 Apr 2020 12:57:37 +0530
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Subject: [PATCH] clk: qcom: ipq8074: disable SW_COLLAPSE for USB GDSCR's
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Change-Id: Id347be781e2bb449bd7cdf05e3535e8ca3c3ffd6
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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(cherry picked from commit 5e100df9c29ed7e5ad12583aa39053f4a9761efe)
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Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
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Change-Id: I17beca334be79d738a35587860847aa0b1f96fa9
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---
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drivers/clk/qcom/gcc-ipq8074.c | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -5066,6 +5066,11 @@ static int gcc_ipq8074_probe(struct plat
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/* SW Workaround for UBI32 Huayra PLL */
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regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
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+ /* Disable SW_COLLAPSE for USB0 GDSCR */
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+ regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
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+ /* Disable SW_COLLAPSE for USB1 GDSCR */
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+ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
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+
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clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
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clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
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&nss_crypto_pll_config);
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