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175 lines
5.9 KiB
Diff
175 lines
5.9 KiB
Diff
From: Frank Wunderlich <linux@fw-web.de>
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To: linux-rockchip@lists.infradead.org
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Cc: Frank Wunderlich <frank-w@public-files.de>,
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Kishon Vijay Abraham I <kishon@ti.com>,
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Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
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Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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Heiko Stuebner <heiko@sntech.de>,
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Philipp Zabel <p.zabel@pengutronix.de>,
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Johan Jonker <jbx6244@gmail.com>,
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Yifeng Zhao <yifeng.zhao@rock-chips.com>,
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Peter Geis <pgwipeout@gmail.com>,
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Michael Riesch <michael.riesch@wolfvision.net>,
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Liang Chen <cl@rock-chips.com>, Simon Xue <xxm@rock-chips.com>,
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Shawn Lin <shawn.lin@rock-chips.com>,
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linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org,
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linux-kernel@vger.kernel.org
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Subject: [PATCH v4 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes
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Date: Sun, 19 Jun 2022 10:26:04 +0200 [thread overview]
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Message-ID: <20220619082605.7935-5-linux@fw-web.de> (raw)
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In-Reply-To: <20220619082605.7935-1-linux@fw-web.de>
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From: Frank Wunderlich <frank-w@public-files.de>
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Add nodes to rk356x devicetree to support PCIe v3.
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Co-developed-by: Peter Geis <pgwipeout@gmail.com>
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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---
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v4:
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- update pcie3 reg/ranges
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v3:
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- fix from Peter: change bus-range and msi-map, msi-map needs
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to start from 0x0
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v2:
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- change to compatible with soc-part
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- change rockchip,bifurcation to vendor unspecific bifurcation
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++
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1 file changed, 122 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -42,6 +42,128 @@
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reg = <0x0 0xfe190200 0x0 0x20>;
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};
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+ pcie30_phy_grf: syscon@fdcb8000 {
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+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
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+ reg = <0x0 0xfdcb8000 0x0 0x10000>;
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+ };
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+
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+ pcie30phy: phy@fe8c0000 {
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+ compatible = "rockchip,rk3568-pcie3-phy";
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+ reg = <0x0 0xfe8c0000 0x0 0x20000>;
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+ #phy-cells = <0>;
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+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
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+ <&cru PCLK_PCIE30PHY>;
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+ clock-names = "refclk_m", "refclk_n", "pclk";
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+ resets = <&cru SRST_PCIE30PHY>;
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+ reset-names = "phy";
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+ rockchip,phy-grf = <&pcie30_phy_grf>;
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+ status = "disabled";
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+ };
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+
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+ pcie3x1: pcie@fe270000 {
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+ compatible = "rockchip,rk3568-pcie";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ bus-range = <0x0 0xf>;
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+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
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+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
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+ <&cru CLK_PCIE30X1_AUX_NDFT>;
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+ clock-names = "aclk_mst", "aclk_slv",
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+ "aclk_dbi", "pclk", "aux";
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+ device_type = "pci";
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+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
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+ <0 0 0 2 &pcie3x1_intc 1>,
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+ <0 0 0 3 &pcie3x1_intc 2>,
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+ <0 0 0 4 &pcie3x1_intc 3>;
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+ linux,pci-domain = <1>;
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+ num-ib-windows = <6>;
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+ num-ob-windows = <2>;
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+ max-link-speed = <3>;
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+ msi-map = <0x0 &gic 0x1000 0x1000>;
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+ num-lanes = <1>;
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+ phys = <&pcie30phy>;
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+ phy-names = "pcie-phy";
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ reg = <0x3 0xc0400000 0x0 0x00400000>,
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+ <0x0 0xfe270000 0x0 0x00010000>,
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+ <0x3 0x7f000000 0x0 0x01000000>;
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+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
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+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
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+ reg-names = "dbi", "apb", "config";
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+ resets = <&cru SRST_PCIE30X1_POWERUP>;
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+ reset-names = "pipe";
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+ /* bifurcation; lane1 when using 1+1 */
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+ status = "disabled";
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+
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+ pcie3x1_intc: legacy-interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
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+ };
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+ };
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+
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+ pcie3x2: pcie@fe280000 {
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+ compatible = "rockchip,rk3568-pcie";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ bus-range = <0x0 0xf>;
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+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
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+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
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+ <&cru CLK_PCIE30X2_AUX_NDFT>;
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+ clock-names = "aclk_mst", "aclk_slv",
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+ "aclk_dbi", "pclk", "aux";
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+ device_type = "pci";
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+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
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+ <0 0 0 2 &pcie3x2_intc 1>,
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+ <0 0 0 3 &pcie3x2_intc 2>,
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+ <0 0 0 4 &pcie3x2_intc 3>;
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+ linux,pci-domain = <2>;
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+ num-ib-windows = <6>;
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+ num-ob-windows = <2>;
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+ max-link-speed = <3>;
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+ msi-map = <0x0 &gic 0x2000 0x1000>;
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+ num-lanes = <2>;
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+ phys = <&pcie30phy>;
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+ phy-names = "pcie-phy";
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ reg = <0x3 0xc0800000 0x0 0x00400000>,
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+ <0x0 0xfe280000 0x0 0x00010000>,
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+ <0x3 0xbf000000 0x0 0x01000000>;
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+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
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+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
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+ reg-names = "dbi", "apb", "config";
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+ resets = <&cru SRST_PCIE30X2_POWERUP>;
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+ reset-names = "pipe";
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+ /* bifurcation; lane0 when using 1+1 */
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+ status = "disabled";
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+
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+ pcie3x2_intc: legacy-interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
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+ };
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+ };
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+
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gmac0: ethernet@fe2a0000 {
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compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe2a0000 0x0 0x10000>;
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