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228 lines
7.5 KiB
Diff
228 lines
7.5 KiB
Diff
From e88f03230dc07aa3293b6aeb078bd27370bb2594 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Wed, 20 Dec 2023 23:17:24 +0100
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Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
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conf
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Rework nss_port5/6 to use the new multiple configuration implementation
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and correctly fix the clocks for these port under some corner case.
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This is particularly relevant for device that have 2.5G or 10G port
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connected to port5 or port 6 on ipq8074. As the parent are shared
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across multiple port it may be required to select the correct
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configuration to accomplish the desired clock. Without this patch such
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port doesn't work in some specific ethernet speed as the clock will be
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set to the wrong frequency as we just select the first configuration for
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the related frequency instead of selecting the best one.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Acked-by: Stephen Boyd <sboyd@kernel.org>
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Link: https://lore.kernel.org/r/20231220221724.3822-4-ansuelsmth@gmail.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 120 +++++++++++++++++++++------------
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1 file changed, 76 insertions(+), 44 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -1677,15 +1677,23 @@ static struct clk_regmap_div nss_port4_t
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},
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};
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-static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
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- F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
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- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
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- F(78125000, P_UNIPHY1_RX, 4, 0, 0),
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- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
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- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
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- F(156250000, P_UNIPHY1_RX, 2, 0, 0),
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- F(312500000, P_UNIPHY1_RX, 1, 0, 0),
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+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
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+ C(P_UNIPHY1_RX, 12.5, 0, 0),
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+ C(P_UNIPHY0_RX, 5, 0, 0),
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+};
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+
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+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
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+ C(P_UNIPHY1_RX, 2.5, 0, 0),
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+ C(P_UNIPHY0_RX, 1, 0, 0),
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+};
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+
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+static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
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+ FMS(19200000, P_XO, 1, 0, 0),
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+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
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+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
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+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
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+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
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+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
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{ }
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};
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@@ -1712,14 +1720,14 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32
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static struct clk_rcg2 nss_port5_rx_clk_src = {
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.cmd_rcgr = 0x68060,
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- .freq_tbl = ftbl_nss_port5_rx_clk_src,
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+ .freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_port5_rx_clk_src",
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.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
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.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_rcg2_fm_ops,
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},
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};
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@@ -1739,15 +1747,23 @@ static struct clk_regmap_div nss_port5_r
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},
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};
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-static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
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- F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
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- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
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- F(78125000, P_UNIPHY1_TX, 4, 0, 0),
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- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
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- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
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- F(156250000, P_UNIPHY1_TX, 2, 0, 0),
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- F(312500000, P_UNIPHY1_TX, 1, 0, 0),
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+static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
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+ C(P_UNIPHY1_TX, 12.5, 0, 0),
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+ C(P_UNIPHY0_TX, 5, 0, 0),
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+};
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+
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+static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
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+ C(P_UNIPHY1_TX, 2.5, 0, 0),
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+ C(P_UNIPHY0_TX, 1, 0, 0),
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+};
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+
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+static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
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+ FMS(19200000, P_XO, 1, 0, 0),
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+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
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+ FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
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+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
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+ FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
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+ FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
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{ }
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};
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@@ -1774,14 +1790,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32
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static struct clk_rcg2 nss_port5_tx_clk_src = {
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.cmd_rcgr = 0x68068,
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- .freq_tbl = ftbl_nss_port5_tx_clk_src,
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+ .freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_port5_tx_clk_src",
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.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
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.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_rcg2_fm_ops,
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},
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};
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@@ -1801,15 +1817,23 @@ static struct clk_regmap_div nss_port5_t
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},
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};
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-static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
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- F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY2_RX, 5, 0, 0),
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- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
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- F(78125000, P_UNIPHY2_RX, 4, 0, 0),
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- F(125000000, P_UNIPHY2_RX, 1, 0, 0),
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- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
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- F(156250000, P_UNIPHY2_RX, 2, 0, 0),
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- F(312500000, P_UNIPHY2_RX, 1, 0, 0),
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+static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
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+ C(P_UNIPHY2_RX, 5, 0, 0),
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+ C(P_UNIPHY2_RX, 12.5, 0, 0),
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+};
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+
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+static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
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+ C(P_UNIPHY2_RX, 1, 0, 0),
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+ C(P_UNIPHY2_RX, 2.5, 0, 0),
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+};
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+
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+static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = {
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+ FMS(19200000, P_XO, 1, 0, 0),
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+ FM(25000000, ftbl_nss_port6_rx_clk_src_25),
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+ FMS(78125000, P_UNIPHY2_RX, 4, 0, 0),
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+ FM(125000000, ftbl_nss_port6_rx_clk_src_125),
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+ FMS(156250000, P_UNIPHY2_RX, 2, 0, 0),
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+ FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
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{ }
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};
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@@ -1831,14 +1855,14 @@ static const struct parent_map gcc_xo_un
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static struct clk_rcg2 nss_port6_rx_clk_src = {
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.cmd_rcgr = 0x68070,
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- .freq_tbl = ftbl_nss_port6_rx_clk_src,
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+ .freq_multi_tbl = ftbl_nss_port6_rx_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_port6_rx_clk_src",
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.parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
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.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_rcg2_fm_ops,
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},
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};
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@@ -1858,15 +1882,23 @@ static struct clk_regmap_div nss_port6_r
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},
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};
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-static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
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- F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY2_TX, 5, 0, 0),
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- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
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- F(78125000, P_UNIPHY2_TX, 4, 0, 0),
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- F(125000000, P_UNIPHY2_TX, 1, 0, 0),
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- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
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- F(156250000, P_UNIPHY2_TX, 2, 0, 0),
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- F(312500000, P_UNIPHY2_TX, 1, 0, 0),
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+static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
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+ C(P_UNIPHY2_TX, 5, 0, 0),
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+ C(P_UNIPHY2_TX, 12.5, 0, 0),
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+};
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+
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+static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
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+ C(P_UNIPHY2_TX, 1, 0, 0),
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+ C(P_UNIPHY2_TX, 2.5, 0, 0),
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+};
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+
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+static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = {
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+ FMS(19200000, P_XO, 1, 0, 0),
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+ FM(25000000, ftbl_nss_port6_tx_clk_src_25),
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+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
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+ FM(125000000, ftbl_nss_port6_tx_clk_src_125),
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+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
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+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
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{ }
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};
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@@ -1888,14 +1920,14 @@ static const struct parent_map gcc_xo_un
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static struct clk_rcg2 nss_port6_tx_clk_src = {
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.cmd_rcgr = 0x68078,
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- .freq_tbl = ftbl_nss_port6_tx_clk_src,
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+ .freq_multi_tbl = ftbl_nss_port6_tx_clk_src,
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.hid_width = 5,
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.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "nss_port6_tx_clk_src",
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.parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
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.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
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- .ops = &clk_rcg2_ops,
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+ .ops = &clk_rcg2_fm_ops,
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},
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};
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