mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-06-12 17:12:04 +08:00
536 lines
13 KiB
Diff
536 lines
13 KiB
Diff
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
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@@ -240,7 +240,7 @@
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#define PLL14 232
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#define PLL14_VOTE 233
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#define PLL18 234
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-#define CE5_SRC 235
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+#define CE5_A_CLK 235
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#define CE5_H_CLK 236
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#define CE5_CORE_CLK 237
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#define CE3_SLEEP_CLK 238
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@@ -283,5 +283,9 @@
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#define EBI2_AON_CLK 281
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#define NSSTCM_CLK_SRC 282
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#define NSSTCM_CLK 283
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+#define NSS_CORE_CLK 284 /* Virtual */
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+#define CE5_A_CLK_SRC 285
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+#define CE5_H_CLK_SRC 286
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+#define CE5_CORE_CLK_SRC 287
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#endif
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--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
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+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
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@@ -163,5 +163,10 @@
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#define NSS_CAL_PRBS_RST_N_RESET 154
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#define NSS_LCKDT_RST_N_RESET 155
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#define NSS_SRDS_N_RESET 156
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+#define CRYPTO_ENG1_RESET 157
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+#define CRYPTO_ENG2_RESET 158
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+#define CRYPTO_ENG3_RESET 159
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+#define CRYPTO_ENG4_RESET 160
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+#define CRYPTO_AHB_RESET 161
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#endif
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -24,6 +24,10 @@
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#include "clk-branch.h"
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#include "clk-hfpll.h"
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#include "reset.h"
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+#include <linux/regulator/nss-volt-ipq806x.h>
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+
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+/* NSS safe parent index which will be used during NSS PLL rate change */
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+static int gcc_ipq806x_nss_safe_parent;
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static struct clk_pll pll0 = {
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.l_reg = 0x30c4,
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@@ -222,7 +226,9 @@ static struct clk_regmap pll14_vote = {
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static struct pll_freq_tbl pll18_freq_tbl[] = {
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NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
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+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
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NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
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+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
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};
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static struct clk_pll pll18 = {
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@@ -244,6 +250,22 @@ static struct clk_pll pll18 = {
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},
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};
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+static struct clk_pll pll11 = {
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+ .l_reg = 0x3184,
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+ .m_reg = 0x3188,
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+ .n_reg = 0x318c,
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+ .config_reg = 0x3194,
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+ .mode_reg = 0x3180,
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+ .status_reg = 0x3198,
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+ .status_bit = 16,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .name = "pll11",
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .ops = &clk_pll_ops,
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+ },
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+};
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+
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enum {
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P_PXO,
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P_PLL8,
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@@ -252,6 +274,7 @@ enum {
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P_CXO,
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P_PLL14,
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P_PLL18,
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+ P_PLL11,
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};
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static const struct parent_map gcc_pxo_pll8_map[] = {
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@@ -319,6 +342,42 @@ static const char * const gcc_pxo_pll8_p
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"pll18",
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};
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+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
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+ { P_PXO, 0 },
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+ { P_PLL8, 4 },
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+ { P_PLL0, 2 },
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+ { P_PLL14, 5 },
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+ { P_PLL18, 1 },
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+ { P_PLL11, 3 },
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+};
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+
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+static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
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+ "pxo",
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+ "pll8_vote",
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+ "pll0_vote",
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+ "pll14",
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+ "pll18",
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+ "pll11"
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+};
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+
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+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
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+ { P_PXO, 0 },
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+ { P_PLL3, 6 },
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+ { P_PLL0, 2 },
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+ { P_PLL14, 5 },
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+ { P_PLL18, 1 },
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+ { P_PLL11, 3 },
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+};
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+
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+static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
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+ "pxo",
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+ "pll3",
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+ "pll0_vote",
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+ "pll14",
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+ "pll18",
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+ "pll11"
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+};
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+
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static struct freq_tbl clk_tbl_gsbi_uart[] = {
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{ 1843200, P_PLL8, 2, 6, 625 },
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{ 3686400, P_PLL8, 2, 12, 625 },
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@@ -2643,7 +2702,9 @@ static const struct freq_tbl clk_tbl_nss
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{ 110000000, P_PLL18, 1, 1, 5 },
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{ 275000000, P_PLL18, 2, 0, 0 },
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{ 550000000, P_PLL18, 1, 0, 0 },
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+ { 600000000, P_PLL18, 1, 0, 0 },
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{ 733000000, P_PLL18, 1, 0, 0 },
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+ { 800000000, P_PLL18, 1, 0, 0 },
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{ }
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};
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@@ -2753,6 +2814,319 @@ static struct clk_dyn_rcg ubi32_core2_sr
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},
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};
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+static const struct freq_tbl clk_tbl_ce5_core[] = {
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+ { 150000000, P_PLL3, 8, 1, 1 },
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+ { 213200000, P_PLL11, 5, 1, 1 },
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+ { }
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+};
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+
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+static struct clk_dyn_rcg ce5_core_src = {
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+ .ns_reg[0] = 0x36C4,
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+ .ns_reg[1] = 0x36C8,
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+ .bank_reg = 0x36C0,
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+ .s[0] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
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+ },
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+ .s[1] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
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+ },
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+ .p[0] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .p[1] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .mux_sel_bit = 0,
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+ .freq_tbl = clk_tbl_ce5_core,
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+ .clkr = {
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+ .enable_reg = 0x36C0,
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+ .enable_mask = BIT(1),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_core_src",
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+ .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
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+ .num_parents = 6,
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+ .ops = &clk_dyn_rcg_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch ce5_core_clk = {
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+ .halt_reg = 0x2FDC,
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+ .halt_bit = 5,
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+ .hwcg_reg = 0x36CC,
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+ .hwcg_bit = 6,
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+ .clkr = {
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+ .enable_reg = 0x36CC,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_core_clk",
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+ .parent_names = (const char *[]){
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+ "ce5_core_src",
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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+ },
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+ },
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+};
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+
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+static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
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+ { 160000000, P_PLL0, 5, 1, 1 },
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+ { 213200000, P_PLL11, 5, 1, 1 },
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+ { }
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+};
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+
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+static struct clk_dyn_rcg ce5_a_clk_src = {
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+ .ns_reg[0] = 0x3d84,
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+ .ns_reg[1] = 0x3d88,
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+ .bank_reg = 0x3d80,
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+ .s[0] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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+ },
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+ .s[1] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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+ },
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+ .p[0] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .p[1] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .mux_sel_bit = 0,
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+ .freq_tbl = clk_tbl_ce5_a_clk,
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+ .clkr = {
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+ .enable_reg = 0x3d80,
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+ .enable_mask = BIT(1),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_a_clk_src",
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+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
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+ .num_parents = 6,
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+ .ops = &clk_dyn_rcg_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch ce5_a_clk = {
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+ .halt_reg = 0x3c20,
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+ .halt_bit = 12,
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+ .hwcg_reg = 0x3d8c,
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+ .hwcg_bit = 6,
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+ .clkr = {
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+ .enable_reg = 0x3d8c,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_a_clk",
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+ .parent_names = (const char *[]){
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+ "ce5_a_clk_src",
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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+ },
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+ },
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+};
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+
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+static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
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+ { 160000000, P_PLL0, 5, 1, 1 },
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+ { 213200000, P_PLL11, 5, 1, 1 },
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+ { }
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+};
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+
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+static struct clk_dyn_rcg ce5_h_clk_src = {
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+ .ns_reg[0] = 0x3c64,
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+ .ns_reg[1] = 0x3c68,
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+ .bank_reg = 0x3c60,
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+ .s[0] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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+ },
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+ .s[1] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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+ },
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+ .p[0] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .p[1] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .mux_sel_bit = 0,
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+ .freq_tbl = clk_tbl_ce5_h_clk,
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+ .clkr = {
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+ .enable_reg = 0x3c60,
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+ .enable_mask = BIT(1),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_h_clk_src",
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+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
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+ .num_parents = 6,
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+ .ops = &clk_dyn_rcg_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch ce5_h_clk = {
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+ .halt_reg = 0x3c20,
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+ .halt_bit = 11,
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+ .hwcg_reg = 0x3c6c,
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+ .hwcg_bit = 6,
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+ .clkr = {
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+ .enable_reg = 0x3c6c,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_h_clk",
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+ .parent_names = (const char *[]){
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+ "ce5_h_clk_src",
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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+ },
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+ },
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+};
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+
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+static int nss_core_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ int ret;
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+
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+ /*
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+ * When ramping up voltage, it needs to be done first. This ensures that
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+ * the volt required will be available when you step up the frequency.
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+ */
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+ ret = nss_ramp_voltage(rate, true);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_dyn_rcg_ops.set_rate(&ubi32_core1_src_clk.clkr.hw, rate,
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+ parent_rate);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_dyn_rcg_ops.set_rate(&ubi32_core2_src_clk.clkr.hw, rate,
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+ parent_rate);
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+
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * When ramping down voltage, it needs to be set first. This ensures
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+ * that the volt required will be available until you step down the
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+ * frequency.
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+ */
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+ ret = nss_ramp_voltage(rate, false);
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+
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+ return ret;
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+}
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+
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+static int
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+nss_core_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate, u8 index)
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+{
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+ int ret;
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+
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+ /*
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+ * When ramping up voltage needs to be done first. This ensures that
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+ * the voltage required will be available when you step up the
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+ * frequency.
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+ */
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+ ret = nss_ramp_voltage(rate, true);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_dyn_rcg_ops.set_rate_and_parent(
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+ &ubi32_core1_src_clk.clkr.hw, rate, parent_rate, index);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_dyn_rcg_ops.set_rate_and_parent(
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+ &ubi32_core2_src_clk.clkr.hw, rate, parent_rate, index);
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+
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * When ramping down voltage needs to be done last. This ensures that
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+ * the voltage required will be available when you step down the
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+ * frequency.
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+ */
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+ ret = nss_ramp_voltage(rate, false);
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+
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+ return ret;
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+}
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+
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+static int nss_core_clk_determine_rate(struct clk_hw *hw,
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+ struct clk_rate_request *req)
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+{
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+ return clk_dyn_rcg_ops.determine_rate(&ubi32_core1_src_clk.clkr.hw,
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+ req);
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+}
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+
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+static unsigned long
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+nss_core_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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+{
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+ return clk_dyn_rcg_ops.recalc_rate(&ubi32_core1_src_clk.clkr.hw,
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+ parent_rate);
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+}
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+
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+static u8 nss_core_clk_get_parent(struct clk_hw *hw)
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+{
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+ return clk_dyn_rcg_ops.get_parent(&ubi32_core1_src_clk.clkr.hw);
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+}
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+
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+static int nss_core_clk_set_parent(struct clk_hw *hw, u8 i)
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+{
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+ int ret;
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+ struct clk_dyn_rcg *rcg;
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+ struct freq_tbl f = { 200000000, P_PLL0, 2, 1, 2 };
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+
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+ /* P_PLL0 is 800 Mhz which needs to be divided for 200 Mhz */
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+ if (i == gcc_ipq806x_nss_safe_parent) {
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+ rcg = to_clk_dyn_rcg(&ubi32_core1_src_clk.clkr.hw);
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+ clk_dyn_configure_bank(rcg, &f);
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+
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+ rcg = to_clk_dyn_rcg(&ubi32_core2_src_clk.clkr.hw);
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+ clk_dyn_configure_bank(rcg, &f);
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+
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+ return 0;
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+ }
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+
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+ ret = clk_dyn_rcg_ops.set_parent(&ubi32_core1_src_clk.clkr.hw, i);
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+ if (ret)
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+ return ret;
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+
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+ return clk_dyn_rcg_ops.set_parent(&ubi32_core2_src_clk.clkr.hw, i);
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+}
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+
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+static const struct clk_ops clk_ops_nss_core = {
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+ .set_rate = nss_core_clk_set_rate,
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+ .set_rate_and_parent = nss_core_clk_set_rate_and_parent,
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+ .determine_rate = nss_core_clk_determine_rate,
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+ .recalc_rate = nss_core_clk_recalc_rate,
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+ .get_parent = nss_core_clk_get_parent,
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+ .set_parent = nss_core_clk_set_parent,
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+};
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+
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+/* Virtual clock for nss core clocks */
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+static struct clk_regmap nss_core_clk = {
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+ .hw.init = &(struct clk_init_data){
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+ .name = "nss_core_clk",
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+ .ops = &clk_ops_nss_core,
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+ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
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+ .num_parents = 5,
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+ .flags = CLK_SET_RATE_PARENT,
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+ },
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+};
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+
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static struct clk_regmap *gcc_ipq806x_clks[] = {
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[PLL0] = &pll0.clkr,
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[PLL0_VOTE] = &pll0_vote,
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@@ -2760,6 +3134,7 @@ static struct clk_regmap *gcc_ipq806x_cl
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[PLL4_VOTE] = &pll4_vote,
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[PLL8] = &pll8.clkr,
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[PLL8_VOTE] = &pll8_vote,
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+ [PLL11] = &pll11.clkr,
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[PLL14] = &pll14.clkr,
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[PLL14_VOTE] = &pll14_vote,
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[PLL18] = &pll18.clkr,
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@@ -2871,9 +3246,16 @@ static struct clk_regmap *gcc_ipq806x_cl
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[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
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[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
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[NSSTCM_CLK] = &nss_tcm_clk.clkr,
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+ [NSS_CORE_CLK] = &nss_core_clk,
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[PLL9] = &hfpll0.clkr,
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[PLL10] = &hfpll1.clkr,
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[PLL12] = &hfpll_l2.clkr,
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+ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
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+ [CE5_A_CLK] = &ce5_a_clk.clkr,
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+ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
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+ [CE5_H_CLK] = &ce5_h_clk.clkr,
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+ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
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+ [CE5_CORE_CLK] = &ce5_core_clk.clkr,
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};
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static const struct qcom_reset_map gcc_ipq806x_resets[] = {
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@@ -3005,6 +3387,11 @@ static const struct qcom_reset_map gcc_i
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[GMAC_CORE3_RESET] = { 0x3cfc, 0 },
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[GMAC_CORE4_RESET] = { 0x3d1c, 0 },
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[GMAC_AHB_RESET] = { 0x3e24, 0 },
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+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
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+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
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+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
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+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
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+ [CRYPTO_AHB_RESET] = { 0x3e10, 0},
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[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
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[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
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[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
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@@ -3080,6 +3467,12 @@ static int gcc_ipq806x_probe(struct plat
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if (!regmap)
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return -ENODEV;
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|
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+ gcc_ipq806x_nss_safe_parent = qcom_find_src_index(&nss_core_clk.hw,
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+ gcc_pxo_pll8_pll14_pll18_pll0_map,
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+ P_PLL0);
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+ if (gcc_ipq806x_nss_safe_parent < 0)
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+ return gcc_ipq806x_nss_safe_parent;
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+
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/* Setup PLL18 static bits */
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regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
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regmap_write(regmap, 0x31b0, 0x3080);
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--- a/drivers/clk/qcom/clk-rcg.c
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+++ b/drivers/clk/qcom/clk-rcg.c
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@@ -805,6 +805,11 @@ static int clk_dyn_rcg_set_rate_and_pare
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return __clk_dyn_rcg_set_rate(hw, rate);
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}
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|
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+void clk_dyn_configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
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+{
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+ configure_bank(rcg, f);
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+}
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+
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const struct clk_ops clk_rcg_ops = {
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.enable = clk_enable_regmap,
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.disable = clk_disable_regmap,
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--- a/drivers/clk/qcom/clk-rcg.h
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|
+++ b/drivers/clk/qcom/clk-rcg.h
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|
@@ -173,4 +173,7 @@ struct clk_rcg_dfs_data {
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|
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
|
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const struct clk_rcg_dfs_data *rcgs,
|
|
size_t len);
|
|
+
|
|
+extern void clk_dyn_configure_bank(struct clk_dyn_rcg *rcg,
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|
+ const struct freq_tbl *f);
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#endif
|