mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-06-10 04:12:05 +08:00
70b6c02432
* ipq806x: fix missing changes in 5.4 for new cpufreq implementation The new cpufreq dedicated driver changed the node structure on how the cache should be defined in the dts. The 5.4 dtsi addition patch has not been updated to follow the new implementation. Fix this to restore correct cache scaling and restore any performance regression. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> * ipq806x: fix missing 1.4ghz cache freq for ipq8065 SoC With the new implementation of the dedicated cpufreq driver, the 1.4 Ghz was only dropped and not added to the ipq8065 SoC. Fix this to improve performance. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> * ipq806x: fix dedicated cpufreq driver 2 small fix for the dedicated cpufreq driver: - Fix index wrongly used as the current cpu - Exit early if a bad freq is detected. In the current state the freq is applied anyway even with invalid state. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Co-authored-by: Ansuel Smith <ansuelsmth@gmail.com>
1025 lines
22 KiB
Diff
1025 lines
22 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -8,6 +8,8 @@
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#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/mfd/qcom-rpm.h>
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+#include <dt-bindings/clock/qcom,rpmcc.h>
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/ {
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#address-cells = <1>;
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@@ -28,6 +30,16 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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+ clocks = <&kraitcc 0>, <&kraitcc 4>;
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+ clock-names = "cpu", "l2";
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+ clock-latency = <100000>;
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+ cpu-supply = <&smb208_s2a>;
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+ operating-points-v2 = <&opp_table0>;
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+ voltage-tolerance = <5>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <10>;
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+ #cooling-cells = <2>;
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+ cpu-idle-states = <&CPU_SPC>;
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};
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cpu1: cpu@1 {
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@@ -38,11 +50,476 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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+ clocks = <&kraitcc 1>, <&kraitcc 4>;
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+ clock-names = "cpu", "l2";
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+ clock-latency = <100000>;
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+ cpu-supply = <&smb208_s2b>;
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+ operating-points-v2 = <&opp_table0>;
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+ voltage-tolerance = <5>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <10>;
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+ #cooling-cells = <2>;
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+ cpu-idle-states = <&CPU_SPC>;
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};
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- L2: l2-cache {
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- compatible = "cache";
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- cache-level = <2>;
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+ idle-states {
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+ CPU_SPC: spc {
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+ compatible = "qcom,idle-state-spc", "arm,idle-state";
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+ status = "disabled";
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+ entry-latency-us = <400>;
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+ exit-latency-us = <900>;
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+ min-residency-us = <3000>;
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+ };
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+ };
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+ };
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+
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+ opp_table_l2: opp_table_l2 {
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+ compatible = "operating-points-v2";
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+
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+ opp-384000000 {
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+ opp-hz = /bits/ 64 <384000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <0>;
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+ };
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+
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+ opp-1000000000 {
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+ opp-hz = /bits/ 64 <1000000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1150000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+ };
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+
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+ opp_table0: opp_table0 {
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+ compatible = "operating-points-v2-kryo-cpu";
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+ nvmem-cells = <&speedbin_efuse>;
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+
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+ opp-384000000 {
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+ opp-hz = /bits/ 64 <384000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1000000>;
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+ opp-microvolt-speed0-pvs1-v0 = <925000>;
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+ opp-microvolt-speed0-pvs2-v0 = <875000>;
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+ opp-microvolt-speed0-pvs3-v0 = <800000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <0>;
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+ };
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+
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+ opp-600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1050000>;
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+ opp-microvolt-speed0-pvs1-v0 = <975000>;
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+ opp-microvolt-speed0-pvs2-v0 = <925000>;
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+ opp-microvolt-speed0-pvs3-v0 = <850000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1100000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1025000>;
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+ opp-microvolt-speed0-pvs2-v0 = <995000>;
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+ opp-microvolt-speed0-pvs3-v0 = <900000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1000000000 {
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+ opp-hz = /bits/ 64 <1000000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1150000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1075000>;
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+ opp-microvolt-speed0-pvs2-v0 = <1025000>;
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+ opp-microvolt-speed0-pvs3-v0 = <950000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1200000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1125000>;
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+ opp-microvolt-speed0-pvs2-v0 = <1075000>;
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+ opp-microvolt-speed0-pvs3-v0 = <1000000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1400000000 {
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+ opp-hz = /bits/ 64 <1400000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1250000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1175000>;
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+ opp-microvolt-speed0-pvs2-v0 = <1125000>;
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+ opp-microvolt-speed0-pvs3-v0 = <1050000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+ };
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+
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+ thermal-zones {
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+ tsens_tz_sensor0 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 0>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor1 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 1>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor2 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 2>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor3 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 3>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor4 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 4>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor5 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 5>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor6 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 6>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor7 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 7>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor8 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 8>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
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+ };
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+ };
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+ };
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+
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+ tsens_tz_sensor9 {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&tsens 9>;
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+
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+ trips {
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+ cpu-critical-hi {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical_high";
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+ };
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+
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+ cpu-config-hi {
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+ temperature = <105000>;
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+ hysteresis = <2000>;
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+ type = "configurable_hi";
|
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+ };
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+
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+ cpu-config-lo {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "configurable_lo";
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+ };
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+
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+ cpu-critical-low {
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+ temperature = <0>;
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+ hysteresis = <2000>;
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+ type = "critical_low";
|
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+ };
|
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+ };
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+ };
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+
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+ tsens_tz_sensor10 {
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+ polling-delay-passive = <0>;
|
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+ polling-delay = <0>;
|
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+ thermal-sensors = <&tsens 10>;
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+
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+ trips {
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+ cpu-critical-hi {
|
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+ temperature = <125000>;
|
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+ hysteresis = <2000>;
|
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+ type = "critical_high";
|
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+ };
|
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+
|
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+ cpu-config-hi {
|
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+ temperature = <105000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "configurable_hi";
|
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+ };
|
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+
|
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+ cpu-config-lo {
|
|
+ temperature = <95000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "configurable_lo";
|
|
+ };
|
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+
|
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+ cpu-critical-low {
|
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+ temperature = <0>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "critical_low";
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|
|
|
|
@@ -93,6 +570,15 @@
|
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};
|
|
};
|
|
|
|
+ fab-scaling {
|
|
+ compatible = "qcom,fab-scaling";
|
|
+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
|
|
+ clock-names = "apps-fab-clk", "ddr-fab-clk";
|
|
+ fab_freq_high = <533000000>;
|
|
+ fab_freq_nominal = <400000000>;
|
|
+ cpu_freq_threshold = <1000000000>;
|
|
+ };
|
|
+
|
|
firmware {
|
|
scm {
|
|
compatible = "qcom,scm-ipq806x", "qcom,scm";
|
|
@@ -120,6 +606,95 @@
|
|
reg-names = "lpass-lpaif";
|
|
};
|
|
|
|
+ L2: l2-cache {
|
|
+ compatible = "qcom,krait-cache", "cache";
|
|
+ cache-level = <2>;
|
|
+ qcom,saw = <&saw_l2>;
|
|
+
|
|
+ clocks = <&kraitcc 4>;
|
|
+ clock-names = "l2";
|
|
+ l2-supply = <&smb208_s1a>;
|
|
+ operating-points-v2 = <&opp_table_l2>;
|
|
+ };
|
|
+
|
|
+ qfprom: qfprom@700000 {
|
|
+ compatible = "qcom,qfprom", "syscon";
|
|
+ reg = <0x700000 0x1000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ status = "okay";
|
|
+ tsens_calib: calib@400 {
|
|
+ reg = <0x400 0xb>;
|
|
+ };
|
|
+ tsens_backup: backup@410 {
|
|
+ reg = <0x410 0xb>;
|
|
+ };
|
|
+ speedbin_efuse: speedbin@0c0 {
|
|
+ reg = <0x0c0 0x4>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rpm: rpm@108000 {
|
|
+ compatible = "qcom,rpm-ipq8064";
|
|
+ reg = <0x108000 0x1000>;
|
|
+ qcom,ipc = <&l2cc 0x8 2>;
|
|
+
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "ack", "err", "wakeup";
|
|
+
|
|
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
|
|
+ clock-names = "ram";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ rpmcc: clock-controller {
|
|
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
+ regulators {
|
|
+ compatible = "qcom,rpm-smb208-regulators";
|
|
+
|
|
+ smb208_s1a: s1a {
|
|
+ regulator-min-microvolt = <1050000>;
|
|
+ regulator-max-microvolt = <1150000>;
|
|
+
|
|
+ qcom,switch-mode-frequency = <1200000>;
|
|
+ };
|
|
+
|
|
+ smb208_s1b: s1b {
|
|
+ regulator-min-microvolt = <1050000>;
|
|
+ regulator-max-microvolt = <1150000>;
|
|
+
|
|
+ qcom,switch-mode-frequency = <1200000>;
|
|
+ };
|
|
+
|
|
+ smb208_s2a: s2a {
|
|
+ regulator-min-microvolt = < 800000>;
|
|
+ regulator-max-microvolt = <1250000>;
|
|
+
|
|
+ qcom,switch-mode-frequency = <1200000>;
|
|
+ };
|
|
+
|
|
+ smb208_s2b: s2b {
|
|
+ regulator-min-microvolt = < 800000>;
|
|
+ regulator-max-microvolt = <1250000>;
|
|
+
|
|
+ qcom,switch-mode-frequency = <1200000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rng@1a500000 {
|
|
+ compatible = "qcom,prng";
|
|
+ reg = <0x1a500000 0x200>;
|
|
+ clocks = <&gcc PRNG_CLK>;
|
|
+ clock-names = "core";
|
|
+ };
|
|
+
|
|
qcom_pinmux: pinmux@800000 {
|
|
compatible = "qcom,ipq8064-pinctrl";
|
|
reg = <0x800000 0x4000>;
|
|
@@ -159,6 +734,15 @@
|
|
};
|
|
};
|
|
|
|
+ i2c4_pins: i2c4_pinmux {
|
|
+ mux {
|
|
+ pins = "gpio12", "gpio13";
|
|
+ function = "gsbi4";
|
|
+ drive-strength = <12>;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
spi_pins: spi_pins {
|
|
mux {
|
|
pins = "gpio18", "gpio19", "gpio21";
|
|
@@ -168,6 +752,53 @@
|
|
};
|
|
};
|
|
|
|
+ nand_pins: nand_pins {
|
|
+ disable {
|
|
+ pins = "gpio34", "gpio35", "gpio36",
|
|
+ "gpio37", "gpio38";
|
|
+ function = "nand";
|
|
+ drive-strength = <10>;
|
|
+ bias-disable;
|
|
+ };
|
|
+
|
|
+ pullups {
|
|
+ pins = "gpio39";
|
|
+ function = "nand";
|
|
+ drive-strength = <10>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ hold {
|
|
+ pins = "gpio40", "gpio41", "gpio42",
|
|
+ "gpio43", "gpio44", "gpio45",
|
|
+ "gpio46", "gpio47";
|
|
+ function = "nand";
|
|
+ drive-strength = <10>;
|
|
+ bias-bus-hold;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mdio0_pins: mdio0_pins {
|
|
+ mux {
|
|
+ pins = "gpio0", "gpio1";
|
|
+ function = "mdio";
|
|
+ drive-strength = <8>;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rgmii2_pins: rgmii2_pins {
|
|
+ mux {
|
|
+ pins = "gpio27", "gpio28", "gpio29",
|
|
+ "gpio30", "gpio31", "gpio32",
|
|
+ "gpio51", "gpio52", "gpio59",
|
|
+ "gpio60", "gpio61", "gpio62";
|
|
+ function = "rgmii2";
|
|
+ drive-strength = <8>;
|
|
+ bias-disable;
|
|
+ };
|
|
+ };
|
|
+
|
|
leds_pins: leds_pins {
|
|
mux {
|
|
pins = "gpio7", "gpio8", "gpio9",
|
|
@@ -229,6 +860,17 @@
|
|
clock-output-names = "acpu1_aux";
|
|
};
|
|
|
|
+ l2cc: clock-controller@2011000 {
|
|
+ compatible = "qcom,kpss-gcc", "syscon";
|
|
+ reg = <0x2011000 0x1000>;
|
|
+ clock-output-names = "acpu_l2_aux";
|
|
+ };
|
|
+
|
|
+ kraitcc: clock-controller {
|
|
+ compatible = "qcom,krait-cc-v1";
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
saw0: regulator@2089000 {
|
|
compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
|
|
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
|
@@ -241,6 +883,17 @@
|
|
regulator;
|
|
};
|
|
|
|
+ saw_l2: regulator@02012000 {
|
|
+ compatible = "qcom,saw2", "syscon";
|
|
+ reg = <0x02012000 0x1000>;
|
|
+ regulator;
|
|
+ };
|
|
+
|
|
+ sic_non_secure: sic-non-secure@12100000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x12100000 0x10000>;
|
|
+ };
|
|
+
|
|
gsbi2: gsbi@12480000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <2>;
|
|
@@ -436,6 +1089,15 @@
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
+ tsens: thermal-sensor@900000 {
|
|
+ compatible = "qcom,ipq8064-tsens";
|
|
+ reg = <0x900000 0x3680>;
|
|
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
|
+ nvmem-cell-names = "calib", "calib_backup";
|
|
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #thermal-sensor-cells = <1>;
|
|
+ };
|
|
+
|
|
tcsr: syscon@1a400000 {
|
|
compatible = "qcom,tcsr-ipq8064", "syscon";
|
|
reg = <0x1a400000 0x100>;
|
|
@@ -448,6 +1110,95 @@
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
+ sfpb_mutex_block: syscon@1200600 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x01200600 0x100>;
|
|
+ };
|
|
+
|
|
+ hs_phy_0: hs_phy_0 {
|
|
+ compatible = "qcom,ipq806x-usb-phy-hs";
|
|
+ reg = <0x110f8800 0x30>;
|
|
+ clocks = <&gcc USB30_0_UTMI_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ ss_phy_0: ss_phy_0 {
|
|
+ compatible = "qcom,ipq806x-usb-phy-ss";
|
|
+ reg = <0x110f8830 0x30>;
|
|
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ usb3_0: usb3@110f8800 {
|
|
+ compatible = "qcom,dwc3", "syscon";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <0x110f8800 0x8000>;
|
|
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
+ clock-names = "core";
|
|
+
|
|
+ ranges;
|
|
+
|
|
+ resets = <&gcc USB30_0_MASTER_RESET>;
|
|
+ reset-names = "master";
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3_0: dwc3@11000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x11000000 0xcd00>;
|
|
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ phys = <&hs_phy_0>, <&ss_phy_0>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ dr_mode = "host";
|
|
+ snps,dis_u3_susphy_quirk;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hs_phy_1: hs_phy_1 {
|
|
+ compatible = "qcom,ipq806x-usb-phy-hs";
|
|
+ reg = <0x100f8800 0x30>;
|
|
+ clocks = <&gcc USB30_1_UTMI_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ ss_phy_1: ss_phy_1 {
|
|
+ compatible = "qcom,ipq806x-usb-phy-ss";
|
|
+ reg = <0x100f8830 0x30>;
|
|
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ usb3_1: usb3@100f8800 {
|
|
+ compatible = "qcom,dwc3", "syscon";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <0x100f8800 0x8000>;
|
|
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
+ clock-names = "core";
|
|
+
|
|
+ ranges;
|
|
+
|
|
+ resets = <&gcc USB30_1_MASTER_RESET>;
|
|
+ reset-names = "master";
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3_1: dwc3@10000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x10000000 0xcd00>;
|
|
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ phys = <&hs_phy_1>, <&ss_phy_1>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ dr_mode = "host";
|
|
+ snps,dis_u3_susphy_quirk;
|
|
+ };
|
|
+ };
|
|
+
|
|
pcie0: pci@1b500000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b500000 0x1000
|
|
@@ -601,6 +1352,167 @@
|
|
perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
+ adm_dma: dma@18300000 {
|
|
+ compatible = "qcom,adm";
|
|
+ reg = <0x18300000 0x100000>;
|
|
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #dma-cells = <1>;
|
|
+
|
|
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+
|
|
+ resets = <&gcc ADM0_RESET>,
|
|
+ <&gcc ADM0_PBUS_RESET>,
|
|
+ <&gcc ADM0_C0_RESET>,
|
|
+ <&gcc ADM0_C1_RESET>,
|
|
+ <&gcc ADM0_C2_RESET>;
|
|
+ reset-names = "clk", "pbus", "c0", "c1", "c2";
|
|
+ qcom,ee = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ nand_controller: nand-controller@1ac00000 {
|
|
+ compatible = "qcom,ipq806x-nand";
|
|
+ reg = <0x1ac00000 0x800>;
|
|
+
|
|
+ clocks = <&gcc EBI2_CLK>,
|
|
+ <&gcc EBI2_AON_CLK>;
|
|
+ clock-names = "core", "aon";
|
|
+
|
|
+ dmas = <&adm_dma 3>;
|
|
+ dma-names = "rxtx";
|
|
+ qcom,cmd-crci = <15>;
|
|
+ qcom,data-crci = <3>;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ nss_common: syscon@03000000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x03000000 0x0000FFFF>;
|
|
+ };
|
|
+
|
|
+ qsgmii_csr: syscon@1bb00000 {
|
|
+ compatible = "syscon";
|
|
+ reg = <0x1bb00000 0x000001FF>;
|
|
+ };
|
|
+
|
|
+ stmmac_axi_setup: stmmac-axi-config {
|
|
+ snps,wr_osr_lmt = <7>;
|
|
+ snps,rd_osr_lmt = <7>;
|
|
+ snps,blen = <16 0 0 0 0 0 0>;
|
|
+ };
|
|
+
|
|
+ mdio0: mdio@37000000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ compatible = "qcom,ipq8064-mdio", "syscon";
|
|
+ reg = <0x37000000 0x200000>;
|
|
+ resets = <&gcc GMAC_CORE1_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+ clocks = <&gcc GMAC_CORE1_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac0: ethernet@37000000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
|
+ reg = <0x37000000 0x200000>;
|
|
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ snps,axi-config = <&stmmac_axi_setup>;
|
|
+ snps,pbl = <32>;
|
|
+ snps,aal = <1>;
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE1_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE1_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac1: ethernet@37200000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
|
+ reg = <0x37200000 0x200000>;
|
|
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ snps,axi-config = <&stmmac_axi_setup>;
|
|
+ snps,pbl = <32>;
|
|
+ snps,aal = <1>;
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE2_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE2_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac2: ethernet@37400000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
|
+ reg = <0x37400000 0x200000>;
|
|
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ snps,axi-config = <&stmmac_axi_setup>;
|
|
+ snps,pbl = <32>;
|
|
+ snps,aal = <1>;
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE3_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE3_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac3: ethernet@37600000 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
|
+ reg = <0x37600000 0x200000>;
|
|
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+
|
|
+ snps,axi-config = <&stmmac_axi_setup>;
|
|
+ snps,pbl = <32>;
|
|
+ snps,aal = <1>;
|
|
+
|
|
+ qcom,nss-common = <&nss_common>;
|
|
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
+
|
|
+ clocks = <&gcc GMAC_CORE4_CLK>;
|
|
+ clock-names = "stmmaceth";
|
|
+
|
|
+ resets = <&gcc GMAC_CORE4_RESET>;
|
|
+ reset-names = "stmmaceth";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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@@ -676,4 +1588,17 @@
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};
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};
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};
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+
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+ sfpb_mutex: sfpb-mutex {
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+ compatible = "qcom,sfpb-mutex";
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+ syscon = <&sfpb_mutex_block 4 4>;
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+
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+ #hwlock-cells = <1>;
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+ };
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+
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+ smem {
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+ compatible = "qcom,smem";
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+ memory-region = <&smem>;
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+ hwlocks = <&sfpb_mutex 3>;
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+ };
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|
};
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