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150 lines
5.3 KiB
Diff
150 lines
5.3 KiB
Diff
From 895bbe5061fe2a6825503f57263a4eff9bb78a3c Mon Sep 17 00:00:00 2001
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Message-Id: <895bbe5061fe2a6825503f57263a4eff9bb78a3c.1500038134.git.chunkeey@googlemail.com>
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In-Reply-To: <941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com>
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References: <d45ae31e888ad858d9f4396cabb4dc32a3f0365e.1500038134.git.chunkeey@googlemail.com>
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<941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com>
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From: Ram Chandra Jangir <rjangir@codeaurora.org>
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Date: Sun, 4 Jun 2017 21:38:21 +0200
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Subject: [PATCH v3 3/3] pinctrl: msm: add support to configure ipq40xx
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GPIO_PULL bits
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To: linux-gpio@vger.kernel.org,
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devicetree@vger.kernel.org
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Cc: Linus Walleij <linus.walleij@linaro.org>,
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Rob Herring <robh+dt@kernel.org>,
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Mark Rutland <mark.rutland@arm.com>
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GPIO_PULL bits configurations in TLMM_GPIO_CFG register
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differs for IPQ40xx from rest of the other qcom SoCs.
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As it does not support the keeper state and therefore can't
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support bias-bus-hold property.
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This patch adds a pull_no_keeper setting which configures the
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msm_gpio_pull bits for ipq40xx. This is required to fix the
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proper configurations of gpio-pull bits for nand pins mux.
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IPQ40xx SoC:
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2'b10: Internal pull up enable.
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2'b11: Unsupport
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For other SoC's:
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2'b10: Keeper
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2'b11: Pull-Up
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Note: Due to pull_no_keeper length, all kerneldoc entries
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in the msm_pinctrl_soc_data struct had to be realigned.
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Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
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---
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drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 +
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drivers/pinctrl/qcom/pinctrl-msm.c | 25 +++++++++++++++++++------
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drivers/pinctrl/qcom/pinctrl-msm.h | 16 +++++++++-------
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3 files changed, 29 insertions(+), 13 deletions(-)
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diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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index 9e7f23d29cda..1979b14b6fc3 100644
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--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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@@ -706,6 +706,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
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.groups = ipq4019_groups,
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.ngroups = ARRAY_SIZE(ipq4019_groups),
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.ngpios = 100,
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+ .pull_no_keeper = true,
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};
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static int ipq4019_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
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index 273badd92561..e5e27d79f5ef 100644
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -202,10 +202,11 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
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return 0;
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}
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-#define MSM_NO_PULL 0
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-#define MSM_PULL_DOWN 1
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-#define MSM_KEEPER 2
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-#define MSM_PULL_UP 3
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+#define MSM_NO_PULL 0
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+#define MSM_PULL_DOWN 1
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+#define MSM_KEEPER 2
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+#define MSM_PULL_UP_NO_KEEPER 2
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+#define MSM_PULL_UP 3
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static unsigned msm_regval_to_drive(u32 val)
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{
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@@ -243,10 +244,16 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
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arg = arg == MSM_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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+ if (pctrl->soc->pull_no_keeper)
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+ return -ENOTSUPP;
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+
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arg = arg == MSM_KEEPER;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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- arg = arg == MSM_PULL_UP;
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+ if (pctrl->soc->pull_no_keeper)
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+ arg = arg == MSM_PULL_UP_NO_KEEPER;
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+ else
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+ arg = arg == MSM_PULL_UP;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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arg = msm_regval_to_drive(arg);
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@@ -309,10 +316,16 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
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arg = MSM_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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+ if (pctrl->soc->pull_no_keeper)
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+ return -ENOTSUPP;
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+
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arg = MSM_KEEPER;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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- arg = MSM_PULL_UP;
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+ if (pctrl->soc->pull_no_keeper)
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+ arg = MSM_PULL_UP_NO_KEEPER;
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+ else
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+ arg = MSM_PULL_UP;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* Check for invalid values */
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diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
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index 54fdd04ce9d5..9b9feea540ff 100644
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--- a/drivers/pinctrl/qcom/pinctrl-msm.h
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
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@@ -99,13 +99,14 @@ struct msm_pingroup {
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/**
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* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
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- * @pins: An array describing all pins the pin controller affects.
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- * @npins: The number of entries in @pins.
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- * @functions: An array describing all mux functions the SoC supports.
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- * @nfunctions: The number of entries in @functions.
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- * @groups: An array describing all pin groups the pin SoC supports.
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- * @ngroups: The numbmer of entries in @groups.
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- * @ngpio: The number of pingroups the driver should expose as GPIOs.
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+ * @pins: An array describing all pins the pin controller affects.
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+ * @npins: The number of entries in @pins.
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+ * @functions: An array describing all mux functions the SoC supports.
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+ * @nfunctions: The number of entries in @functions.
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+ * @groups: An array describing all pin groups the pin SoC supports.
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+ * @ngroups: The numbmer of entries in @groups.
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+ * @ngpio: The number of pingroups the driver should expose as GPIOs.
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+ * @pull_no_keeper: The SoC does not support keeper bias.
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*/
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struct msm_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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@@ -115,6 +116,7 @@ struct msm_pinctrl_soc_data {
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const struct msm_pingroup *groups;
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unsigned ngroups;
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unsigned ngpios;
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+ bool pull_no_keeper;
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};
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int msm_pinctrl_probe(struct platform_device *pdev,
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--
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2.13.2
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