mirror of
https://github.com/coolsnowwolf/lede.git
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179 lines
3.8 KiB
Diff
179 lines
3.8 KiB
Diff
From: Md Sadre Alam <quic_mdalam@quicinc.com>
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To: <broonie@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
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<conor+dt@kernel.org>, <andersson@kernel.org>,
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<konradybcio@kernel.org>, <miquel.raynal@bootlin.com>,
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<richard@nod.at>, <vigneshr@ti.com>,
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<manivannan.sadhasivam@linaro.org>,
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<linux-arm-msm@vger.kernel.org>, <linux-spi@vger.kernel.org>,
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<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
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<linux-mtd@lists.infradead.org>
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Cc: <quic_srichara@quicinc.com>, <quic_varada@quicinc.com>,
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<quic_mdalam@quicinc.com>
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Subject: [PATCH v14 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support
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Date: Wed, 20 Nov 2024 14:45:05 +0530 [thread overview]
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Message-ID: <20241120091507.1404368-8-quic_mdalam@quicinc.com> (raw)
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In-Reply-To: <20241120091507.1404368-1-quic_mdalam@quicinc.com>
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Add SPI NAND support for ipq9574 SoC.
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Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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---
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Change in [v14]
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* No change
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Change in [v13]
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* No change
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Change in [v12]
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* No change
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Change in [v11]
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* No change
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Change in [v10]
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* No change
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Change in [v9]
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* No change
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Change in [v8]
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* No change
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Change in [v7]
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* No change
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Change in [v6]
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* No change
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Change in [v5]
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* No change
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Change in [v4]
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* No change
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Change in [v3]
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* Updated gpio number as per pin control driver
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* Fixed alignment issue
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Change in [v2]
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* Added initial enablement for spi-nand
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Change in [v1]
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* Posted as RFC patch for design review
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.../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++
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2 files changed, 70 insertions(+)
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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index 91e104b0f865..6429a6b3b903 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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@@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state {
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drive-strength = <8>;
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bias-pull-up;
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};
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+
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+ qpic_snand_default_state: qpic-snand-default-state {
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+ clock-pins {
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+ pins = "gpio5";
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+ function = "qspi_clk";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ cs-pins {
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+ pins = "gpio4";
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+ function = "qspi_cs";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ data-pins {
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+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
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+ function = "qspi_data";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+};
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+
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+&qpic_bam {
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+ status = "okay";
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+};
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+
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+&qpic_nand {
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+ pinctrl-0 = <&qpic_snand_default_state>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ nand-ecc-engine = <&qpic_nand>;
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ };
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};
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&usb_0_dwc3 {
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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index d1fd35ebc4a2..45fb26bc9480 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -330,6 +330,33 @@ tcsr: syscon@1937000 {
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reg = <0x01937000 0x21000>;
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};
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+ qpic_bam: dma-controller@7984000 {
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+ compatible = "qcom,bam-v1.7.0";
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+ reg = <0x7984000 0x1c000>;
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+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
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+ clock-names = "bam_clk";
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+ #dma-cells = <1>;
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+ qcom,ee = <0>;
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+ status = "disabled";
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+ };
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+
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+ qpic_nand: spi@79b0000 {
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+ compatible = "qcom,ipq9574-snand";
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+ reg = <0x79b0000 0x10000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&gcc GCC_QPIC_CLK>,
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+ <&gcc GCC_QPIC_AHB_CLK>,
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+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
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+ clock-names = "core", "aon", "iom";
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+ dmas = <&qpic_bam 0>,
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+ <&qpic_bam 1>,
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+ <&qpic_bam 2>;
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+ dma-names = "tx", "rx", "cmd";
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+ status = "disabled";
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+ };
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+
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sdhc_1: mmc@7804000 {
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compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x07804000 0x1000>,
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--
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2.34.1
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