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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
26 lines
730 B
Diff
26 lines
730 B
Diff
From ff74c990c4b671f17d0dfc2c93bae9e23b017472 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 31 Dec 2021 18:42:53 +0100
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Subject: [PATCH 126/137] arm64: dts: ipq8074: add label to cpus
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Add label to cpus node as that makes it easy to add OPP table in SoC model
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specific DTSI as IPQ8074 family has differing clocks and voltages based on
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the specific model.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -29,7 +29,7 @@
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};
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};
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- cpus {
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+ cpus: cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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