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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
30 lines
893 B
Diff
30 lines
893 B
Diff
From 0a36a586424feabf9ce9436379f9d061b7844155 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Thu, 18 Aug 2022 23:25:00 +0200
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Subject: [PATCH 110/137] arm64: dts: qcom: ipq8074: add clocks to APCS
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APCS now has support for providing the APSS clocks as the child device
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for IPQ8074.
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So, add the A53 PLL and XO clocks in order to use APCS as the CPU
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clocksource for APSS scaling.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -704,8 +704,9 @@
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apcs_glb: mailbox@b111000 {
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compatible = "qcom,ipq8074-apcs-apps-global";
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reg = <0x0b111000 0x1000>;
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-
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#clock-cells = <1>;
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+ clocks = <&a53pll>, <&xo>;
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+ clock-names = "pll", "xo";
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#mbox-cells = <1>;
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};
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