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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
62 lines
2.0 KiB
Diff
62 lines
2.0 KiB
Diff
From d2b31da4eae2175ff86f28f596b54abde08d382f Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 9 Jul 2022 00:18:45 +0200
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Subject: [PATCH 102/137] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src
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While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
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IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
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currently broken.
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More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
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clock.
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However after debugging why it was always stuck at 800Mhz, it was figured
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out that its not regmap_mux compatible at all.
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It is a simple mux but it uses RCG2 register layout and control bits, so
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utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
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having to provide a dummy frequency table.
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While we are here, use ARRAY_SIZE for number of parents.
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Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.
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Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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---
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drivers/clk/qcom/apss-ipq6018.c | 13 ++++++-------
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1 file changed, 6 insertions(+), 7 deletions(-)
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--- a/drivers/clk/qcom/apss-ipq6018.c
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+++ b/drivers/clk/qcom/apss-ipq6018.c
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@@ -16,7 +16,7 @@
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#include "clk-regmap.h"
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#include "clk-branch.h"
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#include "clk-alpha-pll.h"
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-#include "clk-regmap-mux.h"
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+#include "clk-rcg.h"
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enum {
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P_XO,
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@@ -33,16 +33,15 @@ static const struct parent_map parents_a
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{ P_APSS_PLL_EARLY, 5 },
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};
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-static struct clk_regmap_mux apcs_alias0_clk_src = {
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- .reg = 0x0050,
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- .width = 3,
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- .shift = 7,
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+static struct clk_rcg2 apcs_alias0_clk_src = {
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+ .cmd_rcgr = 0x0050,
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+ .hid_width = 5,
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.parent_map = parents_apcs_alias0_clk_src_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "apcs_alias0_clk_src",
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.parent_data = parents_apcs_alias0_clk_src,
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- .num_parents = 2,
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- .ops = &clk_regmap_mux_closest_ops,
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+ .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
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+ .ops = &clk_rcg2_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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