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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
50 lines
1.7 KiB
Diff
50 lines
1.7 KiB
Diff
From 9d38e110e23ce0b858ccd67a8a819dc187529a33 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Fri, 8 Jul 2022 23:24:25 +0200
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Subject: [PATCH 101/137] clk: qcom: clk-rcg2: add rcg2 mux ops
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An RCG may act as a mux that switch between 2 parents.
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This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
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the CPU cluster clock just switches between XO and the PLL that feeds it.
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Add the required ops to add support for this special configuration and use
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the generic mux function to determine the rate.
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This way we dont have to keep a essentially dummy frequency table to use
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RCG2 as a mux.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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---
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drivers/clk/qcom/clk-rcg.h | 1 +
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drivers/clk/qcom/clk-rcg2.c | 7 +++++++
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2 files changed, 8 insertions(+)
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--- a/drivers/clk/qcom/clk-rcg.h
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+++ b/drivers/clk/qcom/clk-rcg.h
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@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
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extern const struct clk_ops clk_rcg2_ops;
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extern const struct clk_ops clk_rcg2_floor_ops;
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+extern const struct clk_ops clk_rcg2_mux_closest_ops;
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extern const struct clk_ops clk_edp_pixel_ops;
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extern const struct clk_ops clk_byte_ops;
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extern const struct clk_ops clk_byte2_ops;
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--- a/drivers/clk/qcom/clk-rcg2.c
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+++ b/drivers/clk/qcom/clk-rcg2.c
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@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
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+const struct clk_ops clk_rcg2_mux_closest_ops = {
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+ .determine_rate = __clk_mux_determine_rate_closest,
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+ .get_parent = clk_rcg2_get_parent,
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+ .set_parent = clk_rcg2_set_parent,
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+};
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+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
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+
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struct frac_entry {
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int num;
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int den;
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