mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 14:23:38 +00:00
c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
52 lines
2.0 KiB
Diff
52 lines
2.0 KiB
Diff
From 510f246cf8f6af8c0d7a46d22448b812fd9a14a4 Mon Sep 17 00:00:00 2001
|
|
From: Robert Marko <robimarko@gmail.com>
|
|
Date: Mon, 4 Jul 2022 13:33:18 +0200
|
|
Subject: [PATCH 26/44] arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC
|
|
node
|
|
|
|
The ARM timer is usually considered not part of SoC node, just like
|
|
other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
|
|
|
|
arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
|
|
From schema: dtschema/schemas/simple-bus.yaml
|
|
|
|
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
[bjorn: Moved node after "soc" for alphabetical ordering]
|
|
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
|
|
1 file changed, 8 insertions(+), 8 deletions(-)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
@@ -653,14 +653,6 @@
|
|
};
|
|
};
|
|
|
|
- timer {
|
|
- compatible = "arm,armv8-timer";
|
|
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
- };
|
|
-
|
|
watchdog: watchdog@b017000 {
|
|
compatible = "qcom,kpss-wdt";
|
|
reg = <0xb017000 0x1000>;
|
|
@@ -852,4 +844,12 @@
|
|
status = "disabled";
|
|
};
|
|
};
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv8-timer";
|
|
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
+ };
|
|
};
|