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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
37 lines
1.1 KiB
Diff
37 lines
1.1 KiB
Diff
From 4f0959ded385c8ed518659aa08cedbd83ae0726a Mon Sep 17 00:00:00 2001
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From: Kathiravan T <quic_kathirav@quicinc.com>
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Date: Tue, 8 Feb 2022 21:05:24 +0530
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Subject: [PATCH 11/44] arm64: dts: qcom: ipq8074: enable the GICv2m support
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GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
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which supports upto 32 MSI interrupts. Lets add support for the same.
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -634,9 +634,18 @@
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
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+ ranges = <0 0xb00a000 0xffd>;
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+
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+ v2m@0 {
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+ compatible = "arm,gic-v2m-frame";
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+ msi-controller;
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+ reg = <0x0 0xffd>;
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+ };
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};
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timer {
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