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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
From 187368d2936edad6342151ae1ac34d95dc2de2c1 Mon Sep 17 00:00:00 2001
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From: Chukun Pan <amadeus@jmu.edu.cn>
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Date: Fri, 1 Oct 2021 22:54:21 +0800
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Subject: [PATCH 03/44] arm64: dts: qcom: ipq8074: Add QUP5 I2C node
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Add node to support the QUP5 I2C controller inside of IPQ8074.
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It is exactly the same as QUP2 controllers.
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Some routers like ZTE MF269 use this bus.
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Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20211001145421.18302-1-amadeus@jmu.edu.cn
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -430,6 +430,21 @@
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status = "disabled";
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};
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+ blsp1_i2c5: i2c@78b9000 {
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+ compatible = "qcom,i2c-qup-v2.2.1";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x78b9000 0x600>;
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+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
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+ clock-names = "iface", "core";
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+ clock-frequency = <400000>;
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+ dmas = <&blsp_dma 21>, <&blsp_dma 20>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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+
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blsp1_i2c6: i2c@78ba000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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