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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
49 lines
1.9 KiB
Diff
49 lines
1.9 KiB
Diff
From 13bcdf07cb2ecff5d45d2c141df2539b15211448 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Tue, 30 Nov 2021 18:29:09 +0100
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Subject: [PATCH] PCI: aardvark: Mask all interrupts when unbinding driver
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Ensure that no interrupt can be triggered after driver unbind.
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Link: https://lore.kernel.org/r/20211130172913.9727-8-kabel@kernel.org
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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---
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drivers/pci/controller/pci-aardvark.c | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -1887,6 +1887,27 @@ static int advk_pcie_remove(struct platf
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
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advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
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+ /* Disable MSI */
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+ val = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
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+ val &= ~PCIE_CORE_CTRL2_MSI_ENABLE;
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+ advk_writel(pcie, val, PCIE_CORE_CTRL2_REG);
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+
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+ /* Clear MSI address */
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+ advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);
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+ advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);
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+
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+ /* Mask all interrupts */
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+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
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+ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
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+ advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
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+ advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);
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+
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+ /* Clear all interrupts */
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+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
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+ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
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+ advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
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+ advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
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+
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/* Remove IRQ domains */
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advk_pcie_remove_rp_irq_domain(pcie);
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advk_pcie_remove_msi_irq_domain(pcie);
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