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be692b5939
Revert the SDC "CLK_SET_RATE_GATE" changes to the SDC clock regulator structures. See https://elinux.org/images/b/b8/Elc2013_Clement.pdf > if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count) { > > For this particular clock, setting its rate is possible only if the > clock is ungated (not yet prepared) This fixes the MMC failing to initialize on newer ZyXEL NBG6817 hardware revisions with Kingston MMC. Older revisions should hopefully be unaffected. Check MMC hardware details with: cd /sys/block/mmcblk0/device/ && \ tail -v cid date name manfid fwrev hwrev oemid rev Known problematic MMC names (broken before this commit): * M62704 (dated 12/2018) via myself * M62704 (dated 11/2018) via Drake Stefani Known unaffected MMC names (already working without this commit): * S10004 (dated 12/2015) via slh Now, the MMC properly initializes and later switches to high speed. Thanks to: * Ansuel for maintaining/help with the IPQ806x platform, kernel code * slh for additional debugging and suggestions * dwfreed for confirming newer MMC details, clock frequency * robimarko for device driver debug printing help, clock debugging * Drake for testing and confirmation with their own newer NBG6817 ...and anyone else I missed! Signed-off-by: Shane Synan <digitalcircuit36939@gmail.com> Tested-by: Shane Synan <digitalcircuit36939@gmail.com>
373 lines
9.0 KiB
Diff
373 lines
9.0 KiB
Diff
From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Sun, 7 Feb 2021 17:23:38 +0100
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Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine
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Add missing clk and reset needed for nss additional core and crypto
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engine.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq806x.c | 250 +++++++++++++++++++
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include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +-
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include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +
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3 files changed, 259 insertions(+), 1 deletion(-)
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {
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static struct pll_freq_tbl pll18_freq_tbl[] = {
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NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
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+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
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NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
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+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
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};
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static struct clk_pll pll18 = {
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@@ -245,6 +247,22 @@ static struct clk_pll pll18 = {
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},
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};
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+static struct clk_pll pll11 = {
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+ .l_reg = 0x3184,
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+ .m_reg = 0x3188,
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+ .n_reg = 0x318c,
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+ .config_reg = 0x3194,
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+ .mode_reg = 0x3180,
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+ .status_reg = 0x3198,
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+ .status_bit = 16,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .name = "pll11",
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .ops = &clk_pll_ops,
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+ },
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+};
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+
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enum {
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P_PXO,
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P_PLL8,
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@@ -253,6 +271,7 @@ enum {
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P_CXO,
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P_PLL14,
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P_PLL18,
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+ P_PLL11,
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};
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static const struct parent_map gcc_pxo_pll8_map[] = {
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@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p
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"pll18",
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};
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+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
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+ { P_PXO, 0 },
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+ { P_PLL8, 4 },
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+ { P_PLL0, 2 },
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+ { P_PLL14, 5 },
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+ { P_PLL18, 1 },
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+ { P_PLL11, 3 },
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+};
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+
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+static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
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+ "pxo",
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+ "pll8_vote",
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+ "pll0_vote",
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+ "pll14",
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+ "pll18",
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+ "pll11"
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+};
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+
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+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
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+ { P_PXO, 0 },
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+ { P_PLL3, 6 },
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+ { P_PLL0, 2 },
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+ { P_PLL14, 5 },
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+ { P_PLL18, 1 },
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+ { P_PLL11, 3 },
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+};
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+
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+static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
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+ "pxo",
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+ "pll3",
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+ "pll0_vote",
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+ "pll14",
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+ "pll18",
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+ "pll11"
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+};
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+
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static struct freq_tbl clk_tbl_gsbi_uart[] = {
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{ 1843200, P_PLL8, 2, 6, 625 },
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{ 3686400, P_PLL8, 2, 12, 625 },
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@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc
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{ 20210000, P_PLL8, 1, 1, 19 },
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{ 24000000, P_PLL8, 4, 1, 4 },
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{ 48000000, P_PLL8, 4, 1, 2 },
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+ { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */
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{ 64000000, P_PLL8, 3, 1, 2 },
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{ 96000000, P_PLL8, 4, 0, 0 },
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{ 192000000, P_PLL8, 2, 0, 0 },
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@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss
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{ 110000000, P_PLL18, 1, 1, 5 },
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{ 275000000, P_PLL18, 2, 0, 0 },
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{ 550000000, P_PLL18, 1, 0, 0 },
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+ { 600000000, P_PLL18, 1, 0, 0 },
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{ 733000000, P_PLL18, 1, 0, 0 },
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+ { 800000000, P_PLL18, 1, 0, 0 },
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{ }
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};
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@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr
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},
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};
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+static const struct freq_tbl clk_tbl_ce5_core[] = {
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+ { 150000000, P_PLL3, 8, 1, 1 },
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+ { 213200000, P_PLL11, 5, 1, 1 },
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+ { }
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+};
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+
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+static struct clk_dyn_rcg ce5_core_src = {
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+ .ns_reg[0] = 0x36C4,
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+ .ns_reg[1] = 0x36C8,
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+ .bank_reg = 0x36C0,
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+ .s[0] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
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+ },
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+ .s[1] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
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+ },
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+ .p[0] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .p[1] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .mux_sel_bit = 0,
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+ .freq_tbl = clk_tbl_ce5_core,
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+ .clkr = {
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+ .enable_reg = 0x36C0,
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+ .enable_mask = BIT(1),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_core_src",
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+ .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
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+ .num_parents = 6,
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+ .ops = &clk_dyn_rcg_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch ce5_core_clk = {
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+ .halt_reg = 0x2FDC,
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+ .halt_bit = 5,
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+ .hwcg_reg = 0x36CC,
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+ .hwcg_bit = 6,
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+ .clkr = {
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+ .enable_reg = 0x36CC,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_core_clk",
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+ .parent_names = (const char *[]){
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+ "ce5_core_src",
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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+ },
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+ },
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+};
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+
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+static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
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+ { 160000000, P_PLL0, 5, 1, 1 },
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+ { 213200000, P_PLL11, 5, 1, 1 },
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+ { }
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+};
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+
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+static struct clk_dyn_rcg ce5_a_clk_src = {
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+ .ns_reg[0] = 0x3d84,
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+ .ns_reg[1] = 0x3d88,
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+ .bank_reg = 0x3d80,
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+ .s[0] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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+ },
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+ .s[1] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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+ },
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+ .p[0] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .p[1] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .mux_sel_bit = 0,
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+ .freq_tbl = clk_tbl_ce5_a_clk,
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+ .clkr = {
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+ .enable_reg = 0x3d80,
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+ .enable_mask = BIT(1),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_a_clk_src",
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+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
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+ .num_parents = 6,
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+ .ops = &clk_dyn_rcg_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch ce5_a_clk = {
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+ .halt_reg = 0x3c20,
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+ .halt_bit = 12,
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+ .hwcg_reg = 0x3d8c,
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+ .hwcg_bit = 6,
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+ .clkr = {
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+ .enable_reg = 0x3d8c,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_a_clk",
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+ .parent_names = (const char *[]){
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+ "ce5_a_clk_src",
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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+ },
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+ },
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+};
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+
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+static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
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+ { 160000000, P_PLL0, 5, 1, 1 },
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+ { 213200000, P_PLL11, 5, 1, 1 },
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+ { }
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+};
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+
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+static struct clk_dyn_rcg ce5_h_clk_src = {
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+ .ns_reg[0] = 0x3c64,
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+ .ns_reg[1] = 0x3c68,
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+ .bank_reg = 0x3c60,
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+ .s[0] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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+ },
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+ .s[1] = {
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+ .src_sel_shift = 0,
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+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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+ },
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+ .p[0] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .p[1] = {
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+ .pre_div_shift = 3,
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+ .pre_div_width = 4,
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+ },
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+ .mux_sel_bit = 0,
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+ .freq_tbl = clk_tbl_ce5_h_clk,
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+ .clkr = {
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+ .enable_reg = 0x3c60,
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+ .enable_mask = BIT(1),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_h_clk_src",
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+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
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+ .num_parents = 6,
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+ .ops = &clk_dyn_rcg_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch ce5_h_clk = {
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+ .halt_reg = 0x3c20,
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+ .halt_bit = 11,
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+ .hwcg_reg = 0x3c6c,
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+ .hwcg_bit = 6,
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+ .clkr = {
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+ .enable_reg = 0x3c6c,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ce5_h_clk",
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+ .parent_names = (const char *[]){
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+ "ce5_h_clk_src",
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_SET_RATE_PARENT,
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+ },
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+ },
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+};
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+
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static struct clk_regmap *gcc_ipq806x_clks[] = {
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[PLL0] = &pll0.clkr,
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[PLL0_VOTE] = &pll0_vote,
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@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl
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[PLL4_VOTE] = &pll4_vote,
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[PLL8] = &pll8.clkr,
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[PLL8_VOTE] = &pll8_vote,
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+ [PLL11] = &pll11.clkr,
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[PLL14] = &pll14.clkr,
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[PLL14_VOTE] = &pll14_vote,
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[PLL18] = &pll18.clkr,
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@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl
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[PLL9] = &hfpll0.clkr,
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[PLL10] = &hfpll1.clkr,
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[PLL12] = &hfpll_l2.clkr,
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+ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
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+ [CE5_A_CLK] = &ce5_a_clk.clkr,
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+ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
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+ [CE5_H_CLK] = &ce5_h_clk.clkr,
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+ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
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+ [CE5_CORE_CLK] = &ce5_core_clk.clkr,
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};
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static const struct qcom_reset_map gcc_ipq806x_resets[] = {
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@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i
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[GMAC_CORE3_RESET] = { 0x3cfc, 0 },
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[GMAC_CORE4_RESET] = { 0x3d1c, 0 },
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[GMAC_AHB_RESET] = { 0x3e24, 0 },
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+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
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+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
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+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
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+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
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+ [CRYPTO_AHB_RESET] = { 0x3e10, 0},
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[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
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[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
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[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
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--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
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@@ -240,7 +240,7 @@
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#define PLL14 232
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#define PLL14_VOTE 233
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#define PLL18 234
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-#define CE5_SRC 235
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+#define CE5_A_CLK 235
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#define CE5_H_CLK 236
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#define CE5_CORE_CLK 237
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#define CE3_SLEEP_CLK 238
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@@ -283,5 +283,8 @@
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#define EBI2_AON_CLK 281
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#define NSSTCM_CLK_SRC 282
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#define NSSTCM_CLK 283
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+#define CE5_A_CLK_SRC 285
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+#define CE5_H_CLK_SRC 286
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+#define CE5_CORE_CLK_SRC 287
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#endif
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--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
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+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
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@@ -163,5 +163,10 @@
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#define NSS_CAL_PRBS_RST_N_RESET 154
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#define NSS_LCKDT_RST_N_RESET 155
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#define NSS_SRDS_N_RESET 156
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+#define CRYPTO_ENG1_RESET 157
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+#define CRYPTO_ENG2_RESET 158
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+#define CRYPTO_ENG3_RESET 159
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+#define CRYPTO_ENG4_RESET 160
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+#define CRYPTO_AHB_RESET 161
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#endif
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