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63 lines
2.6 KiB
Diff
63 lines
2.6 KiB
Diff
From 0981de6ff0a072fd25d919e661ac22890a7a1e34 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 1 Jan 2022 18:15:03 +0100
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Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
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Downstream QCA 5.4 kernel defines networking resets which are not present
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in the mainline kernel but are required for the networking drivers.
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So, port the downstream resets and avoid using magic values for mask,
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construct mask for resets which require multiple bits to be set/cleared.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
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include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
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2 files changed, 28 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -4785,6 +4785,20 @@ static const struct qcom_reset_map gcc_i
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[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
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[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
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[GCC_WCSSAON_RESET] = { 0x59010, 0 },
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+ [GCC_PPE_FULL_RESET] = { 0x68014, 0, GENMASK(19, 16) },
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+ [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0, GENMASK(13, 4) | BIT(1) },
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+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
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+ [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0, GENMASK(5, 4) | BIT(1) },
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+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
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+ [GCC_UNIPHY2_SOFT_RESET] = { 0x56204, 0, GENMASK(5, 4) | BIT(1) },
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+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
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+ [GCC_EDMA_HW_RESET] = { 0x68014, 0, GENMASK(21, 20) },
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+ [GCC_NSSPORT1_RESET] = { 0x68014, 0, BIT(24) | GENMASK(1, 0) },
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+ [GCC_NSSPORT2_RESET] = { 0x68014, 0, BIT(25) | GENMASK(3, 2) },
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+ [GCC_NSSPORT3_RESET] = { 0x68014, 0, BIT(26) | GENMASK(5, 4) },
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+ [GCC_NSSPORT4_RESET] = { 0x68014, 0, BIT(27) | GENMASK(9, 8) },
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+ [GCC_NSSPORT5_RESET] = { 0x68014, 0, BIT(28) | GENMASK(11, 10) },
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+ [GCC_NSSPORT6_RESET] = { 0x68014, 0, BIT(29) | GENMASK(13, 12) },
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};
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static const struct of_device_id gcc_ipq8074_match_table[] = {
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--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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@@ -367,5 +367,19 @@
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#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
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#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
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#define GCC_WCSSAON_RESET 132
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+#define GCC_PPE_FULL_RESET 133
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+#define GCC_UNIPHY0_SOFT_RESET 134
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+#define GCC_UNIPHY0_XPCS_RESET 135
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+#define GCC_UNIPHY1_SOFT_RESET 136
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+#define GCC_UNIPHY1_XPCS_RESET 137
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+#define GCC_UNIPHY2_SOFT_RESET 138
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+#define GCC_UNIPHY2_XPCS_RESET 139
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+#define GCC_EDMA_HW_RESET 140
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+#define GCC_NSSPORT1_RESET 141
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+#define GCC_NSSPORT2_RESET 142
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+#define GCC_NSSPORT3_RESET 143
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+#define GCC_NSSPORT4_RESET 144
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+#define GCC_NSSPORT5_RESET 145
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+#define GCC_NSSPORT6_RESET 146
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#endif
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