mirror of
https://github.com/coolsnowwolf/lede.git
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a462d2b757
* target: add phytium support * kernel/video: add phytium platform ARM GPU support * config: add EFI support to phytium armv8 * target: phytium: remove rtl8821cs driver * target: phytium: refresh dts
358 lines
13 KiB
C
358 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Driver for Phytium Multimedia Card Interface
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*
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* Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
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*/
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#ifndef __PHYTIUM_MCI_H
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#define __PHYTIUM_MCI_H
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#include <linux/scatterlist.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/mmc/host.h>
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/*------------------------------------------------------*/
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/* Common Definition */
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/*------------------------------------------------------*/
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#define MAX_BD_NUM 128
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#define SD_BLOCK_SIZE 512
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#define MCI_BUS_1BITS 0x0
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#define MCI_BUS_4BITS 0x1
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#define MCI_BUS_8BITS (0x1 << 16)
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#define MCI_SD_DRV_VALUE 0
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#define MCI_SD_SAMP_VALUE_MAX 0
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#define MCI_SD_SAMP_VALUE_MIN 0
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#define MCI_TIMEOUT_CMD_VALUE 0xFFFFFFFF
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#define MCI_POWER_ON 1
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#define MCI_POWER_OFF 0
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#define MCI_PREPARE_FLAG (0x1 << 0)
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#define MCI_ASYNC_FLAG (0x1 << 1)
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#define MCI_MMAP_FLAG (0x1 << 2)
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#define MCI_CMD_TIMEOUT (HZ/10 * 50) /* 100ms x5 */
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#define MCI_DATA_TIMEOUT (HZ * 10) /* 1000ms x5 */
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#define MCI_CMD_TYPE_ADTC 0x2
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#define MCI_F_MIN 400000
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#define MCI_F_MAX 50000000
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#define MCI_CLK 1200000000
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#define MCI_REALEASE_MEM 0x1
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#define MCI_MAX_FIFO_CNT 0x800
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/* FIFOTH register defines */
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#define MCI_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
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((r) & 0xFFF) << 16 | ((t) & 0xFFF))
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/* Card read threshold */
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#define MCI_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
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#define MCI_CARD_WR_THR_EN BIT(2)
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#define MCI_CARD_RD_THR_EN BIT(0)
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/*----------------------------------------------------------------------*/
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/* Register Offset */
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/*----------------------------------------------------------------------*/
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#define MCI_CNTRL 0x00 /* the controller config reg */
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#define MCI_PWREN 0x04 /* the power enable reg */
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#define MCI_CLKDIV 0x08 /* the clock divider reg */
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#define MCI_CLKENA 0x10 /* the clock enable reg */
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#define MCI_TMOUT 0x14 /* the timeout reg */
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#define MCI_CTYPE 0x18 /* the card type reg */
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#define MCI_BLKSIZ 0x1C /* the block size reg */
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#define MCI_BYTCNT 0x20 /* the byte count reg */
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#define MCI_INT_MASK 0x24 /* the interrupt mask reg */
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#define MCI_CMDARG 0x28 /* the command argument reg */
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#define MCI_CMD 0x2C /* the command reg */
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#define MCI_RESP0 0x30 /* the response reg0 */
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#define MCI_RESP1 0x34 /* the response reg1 */
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#define MCI_RESP2 0x38 /* the response reg2 */
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#define MCI_RESP3 0X3C /* the response reg3 */
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#define MCI_MASKED_INTS 0x40 /* the masked interrupt status reg */
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#define MCI_RAW_INTS 0x44 /* the raw interrupt status reg */
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#define MCI_STATUS 0x48 /* the status reg */
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#define MCI_FIFOTH 0x4C /* the FIFO threshold watermark reg */
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#define MCI_CARD_DETECT 0x50 /* the card detect reg */
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#define MCI_CARD_WRTPRT 0x54 /* the card write protect reg */
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#define MCI_CCLK_RDY 0x58 /* first div is ready? 1:ready,0:not ready*/
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#define MCI_TRAN_CARD_CNT 0x5C /* the transferred CIU card byte count reg */
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#define MCI_TRAN_FIFO_CNT 0x60 /* the transferred host to FIFO byte count reg */
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#define MCI_DEBNCE 0x64 /* the debounce count reg */
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#define MCI_UID 0x68 /* the user ID reg */
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#define MCI_VID 0x6C /* the controller version ID reg */
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#define MCI_HWCONF 0x70 /* the hardware configuration reg */
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#define MCI_UHS_REG 0x74 /* the UHS-I reg */
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#define MCI_CARD_RESET 0x78 /* the card reset reg */
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#define MCI_BUS_MODE 0x80 /* the bus mode reg */
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#define MCI_DESC_LIST_ADDRL 0x88 /* the descriptor list low base address reg */
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#define MCI_DESC_LIST_ADDRH 0x8C /* the descriptor list high base address reg */
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#define MCI_DMAC_STATUS 0x90 /* the internal DMAC status reg */
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#define MCI_DMAC_INT_ENA 0x94 /* the internal DMAC interrupt enable reg */
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#define MCI_CUR_DESC_ADDRL 0x98 /* the current host descriptor low address reg */
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#define MCI_CUR_DESC_ADDRH 0x9C /* the current host descriptor high address reg */
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#define MCI_CUR_BUF_ADDRL 0xA0 /* the current buffer low address reg */
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#define MCI_CUR_BUF_ADDRH 0xA4 /* the current buffer high address reg */
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#define MCI_CARD_THRCTL 0x100 /* the card threshold control reg */
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#define MCI_UHS_REG_EXT 0x108 /* the UHS register extension */
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#define MCI_EMMC_DDR_REG 0x10C /* the EMMC DDR reg */
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#define MCI_ENABLE_SHIFT 0x110 /* the enable phase shift reg */
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#define MCI_DATA 0x200 /* the data FIFO access */
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/* Command register defines */
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#define MCI_CMD_START BIT(31)
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#define MCI_CMD_USE_HOLD_REG BIT(29)
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#define MCI_CMD_VOLT_SWITCH BIT(28)
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#define MCI_CMD_CCS_EXP BIT(23)
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#define MCI_CMD_CEATA_RD BIT(22)
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#define MCI_CMD_UPD_CLK BIT(21)
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#define MCI_CMD_INIT BIT(15)
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#define MCI_CMD_STOP BIT(14)
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#define MCI_CMD_PRV_DAT_WAIT BIT(13)
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#define MCI_CMD_SEND_STOP BIT(12)
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#define MCI_CMD_STRM_MODE BIT(11)
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#define MCI_CMD_DAT_WR BIT(10)
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#define MCI_CMD_DAT_EXP BIT(9)
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#define MCI_CMD_RESP_CRC BIT(8)
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#define MCI_CMD_RESP_LONG BIT(7)
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#define MCI_CMD_RESP_EXP BIT(6)
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#define MCI_CMD_INDX(n) ((n) & 0x1F)
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/*------------------------------------------------------*/
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/* Register Mask */
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/*------------------------------------------------------*/
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/* MCI_CNTRL mask */
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#define MCI_CNTRL_CONTROLLER_RESET (0x1 << 0) /* RW */
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#define MCI_CNTRL_FIFO_RESET (0x1 << 1) /* RW */
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#define MCI_CNTRL_DMA_RESET (0x1 << 2) /* RW */
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#define MCI_CNTRL_RES (0x1 << 3) /* */
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#define MCI_CNTRL_INT_ENABLE (0x1 << 4) /* RW */
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#define MCI_CNTRL_DMA_ENABLE (0x1 << 5) /* RW */
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#define MCI_CNTRL_READ_WAIT (0x1 << 6) /* RW */
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#define MCI_CNTRL_SEND_IRQ_RESPONSE (0x1 << 7) /* RW */
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#define MCI_CNTRL_ABORT_READ_DATA (0x1 << 8) /* RW */
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#define MCI_CNTRL_ENDIAN (0x1 << 11) /* RW */
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//#define MCI_CNTRL_CARD_VOLTAGE_A (0xF << 16) /* RW */
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//#define MCI_CNTRL_CARD_VOLTAGE_B (0xF << 20) /* RW */
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#define MCI_CNTRL_ENABLE_OD_PULLUP (0x1 << 24) /* RW */
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#define MCI_CNTRL_USE_INTERNAL_DMAC (0x1 << 25) /* RW */
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/* MCI_PWREN mask */
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#define MCI_PWREN_ENABLE (0x1 << 0) /* RW */
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/* MCI_CLKENA mask */
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#define MCI_CLKENA_CCLK_ENABLE (0x1 << 0) /* RW */
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#define MCI_CLKENA_CCLK_LOW_POWER (0x1 << 16) /* RW */
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#define MCI_EXT_CLK_ENABLE (0x1 << 1)
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/* MCI_INT_MASK mask */
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#define MCI_INT_MASK_CD (0x1 << 0) /* RW */
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#define MCI_INT_MASK_RE (0x1 << 1) /* RW */
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#define MCI_INT_MASK_CMD (0x1 << 2) /* RW */
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#define MCI_INT_MASK_DTO (0x1 << 3) /* RW */
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#define MCI_INT_MASK_TXDR (0x1 << 4) /* RW */
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#define MCI_INT_MASK_RXDR (0x1 << 5) /* RW */
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#define MCI_INT_MASK_RCRC (0x1 << 6) /* RW */
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#define MCI_INT_MASK_DCRC (0x1 << 7) /* RW */
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#define MCI_INT_MASK_RTO (0x1 << 8) /* RW */
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#define MCI_INT_MASK_DRTO (0x1 << 9) /* RW */
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#define MCI_INT_MASK_HTO (0x1 << 10) /* RW */
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#define MCI_INT_MASK_FRUN (0x1 << 11) /* RW */
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#define MCI_INT_MASK_HLE (0x1 << 12) /* RW */
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#define MCI_INT_MASK_SBE_BCI (0x1 << 13) /* RW */
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#define MCI_INT_MASK_ACD (0x1 << 14) /* RW */
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#define MCI_INT_MASK_EBE (0x1 << 15) /* RW */
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#define MCI_INT_MASK_SDIO (0x1 << 16) /* RW */
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/* MCI_MASKED_INTS mask */
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#define MCI_MASKED_INTS_CD (0x1 << 0) /* RO */
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#define MCI_MASKED_INTS_RE (0x1 << 1) /* RO */
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#define MCI_MASKED_INTS_CMD (0x1 << 2) /* RO */
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#define MCI_MASKED_INTS_DTO (0x1 << 3) /* RO */
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#define MCI_MASKED_INTS_TXDR (0x1 << 4) /* RO */
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#define MCI_MASKED_INTS_RXDR (0x1 << 5) /* RO */
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#define MCI_MASKED_INTS_RCRC (0x1 << 6) /* RO */
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#define MCI_MASKED_INTS_DCRC (0x1 << 7) /* RO */
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#define MCI_MASKED_INTS_RTO (0x1 << 8) /* RO */
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#define MCI_MASKED_INTS_DRTO (0x1 << 9) /* RO */
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#define MCI_MASKED_INTS_HTO (0x1 << 10) /* RO */
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#define MCI_MASKED_INTS_FRUN (0x1 << 11) /* RO */
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#define MCI_MASKED_INTS_HLE (0x1 << 12) /* RO */
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#define MCI_MASKED_INTS_SBE_BCI (0x1 << 13) /* RO */
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#define MCI_MASKED_INTS_ACD (0x1 << 14) /* RO */
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#define MCI_MASKED_INTS_EBE (0x1 << 15) /* RO */
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#define MCI_MASKED_INTS_SDIO (0x1 << 16) /* RO */
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/* MCI_RAW_INTS mask */
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#define MCI_RAW_INTS_CD (0x1 << 0) /* W1C */
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#define MCI_RAW_INTS_RE (0x1 << 1) /* W1C */
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#define MCI_RAW_INTS_CMD (0x1 << 2) /* W1C */
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#define MCI_RAW_INTS_DTO (0x1 << 3) /* W1C */
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#define MCI_RAW_INTS_TXDR (0x1 << 4) /* W1C */
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#define MCI_RAW_INTS_RXDR (0x1 << 5) /* W1C */
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#define MCI_RAW_INTS_RCRC (0x1 << 6) /* W1C */
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#define MCI_RAW_INTS_DCRC (0x1 << 7) /* W1C */
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#define MCI_RAW_INTS_RTO (0x1 << 8) /* W1C */
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#define MCI_RAW_INTS_DRTO (0x1 << 9) /* W1C */
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#define MCI_RAW_INTS_HTO (0x1 << 10) /* W1C */
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#define MCI_RAW_INTS_FRUN (0x1 << 11) /* W1C */
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#define MCI_RAW_INTS_HLE (0x1 << 12) /* W1C */
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#define MCI_RAW_INTS_SBE_BCI (0x1 << 13) /* W1C */
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#define MCI_RAW_INTS_ACD (0x1 << 14) /* W1C */
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#define MCI_RAW_INTS_EBE (0x1 << 15) /* W1C */
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#define MCI_RAW_INTS_SDIO (0x1 << 16) /* W1C */
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/* MCI_STATUS mask */
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#define MCI_STATUS_FIFO_RX (0x1 << 0) /* RO */
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#define MCI_STATUS_FIFO_TX (0x1 << 1) /* RO */
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#define MCI_STATUS_FIFO_EMPTY (0x1 << 2) /* RO */
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#define MCI_STATUS_FIFO_FULL (0x1 << 3) /* RO */
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#define MCI_STATUS_CARD_STATUS (0x1 << 8) /* RO */
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#define MCI_STATUS_CARD_BUSY (0x1 << 9) /* RO */
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#define MCI_STATUS_DATA_BUSY (0x1 << 10) /* RO */
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#define MCI_STATUS_RESPOSE_INDEX_OFFSET (11)
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#define MCI_STATUS_RESPOSE_INDEX_MASK (0x3f << MCI_STATUS_RESPOSE_INDEX_OFFSET) /* RO */
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#define MCI_STATUS_RESPOSE_INDEX(reg) (((reg) & MCI_STATUS_RESPOSE_INDEX_MASK) >> MCI_STATUS_RESPOSE_INDEX_OFFSET)
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#define MCI_STATUS_DMA_ACK (0x1 << 31) /* RO */
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#define MCI_STATUS_DMA_REQ (0x1 << 32) /* RO */
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/* MCI_UHS_REG mask */
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#define MCI_UHS_REG_VOLT (0x1 << 0) /* RW */
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#define MCI_UHS_REG_DDR (0x1 << 16) /* RW */
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/* MCI_CARD_RESET mask */
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#define MCI_CARD_RESET_ENABLE (0x1 << 0) /* RW */
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/* MCI_BUS_MODE mask */
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#define MCI_BUS_MODE_SWR (0x1 << 0) /* RW */
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#define MCI_BUS_MODE_FB (0x1 << 1) /* RW */
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#define MCI_BUS_MODE_DE (0x1 << 7) /* RW */
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/* MCI_DMAC_STATUS mask */
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#define MCI_DMAC_STATUS_TI (0x1 << 0) /* RW */
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#define MCI_DMAC_STATUS_RI (0x1 << 1) /* RW */
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#define MCI_DMAC_STATUS_FBE (0x1 << 2) /* RW */
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#define MCI_DMAC_STATUS_DU (0x1 << 4) /* RW */
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#define MCI_DMAC_STATUS_NIS (0x1 << 8) /* RW */
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#define MCI_DMAC_STATUS_AIS (0x1 << 9) /* RW */
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/* MCI_DMAC_INT_ENA mask */
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#define MCI_DMAC_INT_ENA_TI (0x1 << 0) /* RW */
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#define MCI_DMAC_INT_ENA_RI (0x1 << 1) /* RW */
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#define MCI_DMAC_INT_ENA_FBE (0x1 << 2) /* RW */
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#define MCI_DMAC_INT_ENA_DU (0x1 << 4) /* RW */
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#define MCI_DMAC_INT_ENA_CES (0x1 << 5) /* RW */
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#define MCI_DMAC_INT_ENA_NIS (0x1 << 8) /* RW */
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#define MCI_DMAC_INT_ENA_AIS (0x1 << 9) /* RW */
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/* MCI_CARD_THRCTL mask */
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#define MCI_CARD_THRCTL_CARDRD (0x1 << 0) /* RW */
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#define MCI_CARD_THRCTL_BUSY_CLR (0x1 << 1) /* RW */
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#define MCI_CARD_THRCTL_CARDWR (0x1 << 2) /* RW */
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/* MCI_UHS_REG_EXT mask */
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#define MCI_UHS_REG_EXT_MMC_VOLT (0x1 << 0) /* RW */
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#define MCI_UHS_REG_EXT_CLK_ENA (0x1 << 1) /* RW */
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/* MCI_EMMC_DDR_REG mask */
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#define MCI_EMMC_DDR_CYCLE (0x1 << 0) /* RW */
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/*--------------------------------------*/
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/* Structure Type */
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/*--------------------------------------*/
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/* Maximum segments assuming a 512KiB maximum requisition */
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/* size and a minimum4KiB page size. */
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#define MCI_MAX_SEGS 128
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/* ADMA2 64-bit DMA descriptor size */
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#define ADMA2_64_DESC_SZ 32
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/* mmc request timeout 5000ms */
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#define MMC_REQ_TIMEOUT_MS 5000
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/* Each descriptor can transfer up to 4KB of data in chained mode */
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/*ADMA2 64-bit descriptor.*/
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struct phytium_adma2_64_desc {
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u32 attribute;
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#define IDMAC_DES0_DIC BIT(1)
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#define IDMAC_DES0_LD BIT(2)
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#define IDMAC_DES0_FD BIT(3)
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#define IDMAC_DES0_CH BIT(4)
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#define IDMAC_DES0_ER BIT(5)
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#define IDMAC_DES0_CES BIT(30)
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#define IDMAC_DES0_OWN BIT(31)
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u32 NON1;
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u32 len;
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u32 NON2;
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u32 addr_lo; /* Lower 32-bits of Buffer Address Pointer 1*/
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u32 addr_hi; /* Upper 32-bits of Buffer Address Pointer 1*/
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u32 desc_lo; /* Lower 32-bits of Next Descriptor Address */
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u32 desc_hi; /* Upper 32-bits of Next Descriptor Address */
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} __packed __aligned(4);
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struct phytium_mci_dma {
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struct scatterlist *sg; /* I/O scatter list */
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/* ADMA descriptor table, pointer to adma_table array */
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struct phytium_adma2_64_desc *adma_table;
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/* Mapped ADMA descr. table, the physical address of adma_table array */
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dma_addr_t adma_addr;
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unsigned int desc_sz; /* ADMA descriptor size */
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};
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enum adtc_t {
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COMMOM_ADTC = 0,
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BLOCK_RW_ADTC = 1
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};
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struct phytium_mci_host {
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struct device *dev;
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struct mmc_host *mmc;
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u32 caps;
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u32 caps2;
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spinlock_t lock;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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int error;
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void __iomem *base; /* host base address */
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void *adma_table1;
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dma_addr_t adma_addr1;
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struct phytium_mci_dma dma_rx; /* dma channel */
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struct phytium_mci_dma dma_tx; /* dma channel */
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struct phytium_mci_dma dma; /* dma channel */
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u64 dma_mask;
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bool vqmmc_enabled;
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u32 *sg_virt_addr;
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enum adtc_t adtc_type; /* 0:common adtc cmd; 1:block r/w adtc cmd;*/
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struct timer_list hotplug_timer;
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struct timer_list timeout_timer;
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struct delayed_work req_timeout;
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int irq; /* host interrupt */
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u32 current_rca; /*the current rca value*/
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u32 current_ios_clk;
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u32 is_use_dma;
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u32 is_device_x100;
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struct clk *src_clk; /* phytium_mci source clock */
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unsigned long clk_rate;
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unsigned long clk_div;
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unsigned long irq_flags;
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unsigned long flags;
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#define MCI_CARD_NEED_INIT 1
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};
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int phytium_mci_common_probe(struct phytium_mci_host *host);
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void phytium_mci_deinit_hw(struct phytium_mci_host *host);
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int phytium_mci_runtime_suspend(struct device *dev);
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int phytium_mci_runtime_resume(struct device *dev);
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int phytium_mci_resume(struct device *dev);
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int phytium_mci_suspend(struct device *dev);
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#endif /* __PHYTIUM_MCI_HW_H */
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