lede/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch
Shane Synan be692b5939 ipq806x: revert SDC clock changes for NBG6817 MMC
Revert the SDC "CLK_SET_RATE_GATE" changes to the SDC clock regulator
structures.

See https://elinux.org/images/b/b8/Elc2013_Clement.pdf
> if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count) {
>
> For this particular clock, setting its rate is possible only if the
> clock is ungated (not yet prepared)

This fixes the MMC failing to initialize on newer ZyXEL NBG6817
hardware revisions with Kingston MMC.  Older revisions should
hopefully be unaffected.

Check MMC hardware details with:
cd /sys/block/mmcblk0/device/ && \
  tail -v cid date name manfid fwrev hwrev oemid rev

Known problematic MMC names (broken before this commit):
* M62704 (dated 12/2018) via myself
* M62704 (dated 11/2018) via Drake Stefani

Known unaffected MMC names (already working without this commit):
* S10004 (dated 12/2015) via slh

Now, the MMC properly initializes and later switches to high speed.

Thanks to:
* Ansuel for maintaining/help with the IPQ806x platform, kernel code
* slh for additional debugging and suggestions
* dwfreed for confirming newer MMC details, clock frequency
* robimarko for device driver debug printing help, clock debugging
* Drake for testing and confirmation with their own newer NBG6817
...and anyone else I missed!

Signed-off-by: Shane Synan <digitalcircuit36939@gmail.com>
Tested-by: Shane Synan <digitalcircuit36939@gmail.com>
2021-12-16 09:22:06 +08:00

100 lines
2.9 KiB
Diff

From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sun, 7 Feb 2021 16:52:56 +0100
Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag
Some flag are missing from the original code.
These clk can't be set using the protected-clock proprities as they
cause the malfunction of the serial interface.
These clks are needed for the rpm interface to work proprely or the
cpu regulators starts to fail as soon as they are disabled by the
kernel.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -65,6 +65,7 @@ static struct clk_pll pll3 = {
.parent_names = (const char *[]){ "pxo" },
.num_parents = 1,
.ops = &clk_pll_ops,
+ .flags = CLK_IS_CRITICAL,
},
};
@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk =
.parent_names = (const char *[]){ "gsbi4_qup_src" },
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk =
.parent_names = (const char *[]){ "gsbi7_qup_src" },
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
+ .flags = CLK_IGNORE_UNUSED,
},
},
};
@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
+ .flags = CLK_SET_RATE_GATE,
},
}
};
@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr
.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
+ CLK_IGNORE_UNUSED,
},
},
};
@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr
.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
+ CLK_IGNORE_UNUSED,
},
},
};