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be692b5939
Revert the SDC "CLK_SET_RATE_GATE" changes to the SDC clock regulator structures. See https://elinux.org/images/b/b8/Elc2013_Clement.pdf > if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count) { > > For this particular clock, setting its rate is possible only if the > clock is ungated (not yet prepared) This fixes the MMC failing to initialize on newer ZyXEL NBG6817 hardware revisions with Kingston MMC. Older revisions should hopefully be unaffected. Check MMC hardware details with: cd /sys/block/mmcblk0/device/ && \ tail -v cid date name manfid fwrev hwrev oemid rev Known problematic MMC names (broken before this commit): * M62704 (dated 12/2018) via myself * M62704 (dated 11/2018) via Drake Stefani Known unaffected MMC names (already working without this commit): * S10004 (dated 12/2015) via slh Now, the MMC properly initializes and later switches to high speed. Thanks to: * Ansuel for maintaining/help with the IPQ806x platform, kernel code * slh for additional debugging and suggestions * dwfreed for confirming newer MMC details, clock frequency * robimarko for device driver debug printing help, clock debugging * Drake for testing and confirmation with their own newer NBG6817 ...and anyone else I missed! Signed-off-by: Shane Synan <digitalcircuit36939@gmail.com> Tested-by: Shane Synan <digitalcircuit36939@gmail.com> |
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| arc770 | ||
| archs38 | ||
| armvirt | ||
| at91 | ||
| ath25 | ||
| ath79 | ||
| bcm27xx | ||
| bcm47xx | ||
| bcm53xx | ||
| bcm63xx | ||
| bcm4908 | ||
| bmips | ||
| gemini | ||
| generic | ||
| imx6 | ||
| ipq40xx | ||
| ipq60xx | ||
| ipq806x | ||
| ipq807x | ||
| kirkwood | ||
| lantiq | ||
| layerscape | ||
| malta | ||
| mediatek | ||
| mpc85xx | ||
| mvebu | ||
| mxs | ||
| octeon | ||
| octeontx | ||
| omap | ||
| oxnas | ||
| pistachio | ||
| ramips | ||
| realtek | ||
| rockchip | ||
| sunxi | ||
| tegra | ||
| uml | ||
| x86 | ||
| zynq | ||
| Makefile | ||