mirror of
https://github.com/coolsnowwolf/lede.git
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431 lines
7.2 KiB
Plaintext
431 lines
7.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "mt7981.dtsi"
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/ {
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aliases {
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serial0 = &uart0;
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led-boot = &led_system_orange;
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led-failsafe = &led_system_blue;
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led-running = &led_system_blue;
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led-upgrade = &led_system_orange;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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reg = <0 0x40000000 0 0x10000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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};
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mesh {
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label = "mesh";
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linux,code = <BTN_9>;
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linux,input-type = <EV_SW>;
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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};
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};
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leds: leds {
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compatible = "gpio-leds";
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led_system_blue: system_blue {
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label = "blue:system";
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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led_system_orange: system_orange {
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label = "orange:system";
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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};
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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&mdio_bus {
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switch: switch@0 {
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compatible = "mediatek,mt7531";
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reg = <31>;
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reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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};
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mfd: mfd@1 {
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compatible = "airoha,an8855-mfd";
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reg = <1>;
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};
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};
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&mfd {
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efuse {
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compatible = "airoha,an8855-efuse";
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#nvmem-cell-cells = <0>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
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reg = <0xc 0x4>;
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};
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shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
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reg = <0x10 0x4>;
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};
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shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
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reg = <0x14 0x4>;
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};
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shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
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reg = <0x18 0x4>;
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};
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shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
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reg = <0x1c 0x4>;
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};
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shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
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reg = <0x20 0x4>;
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};
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shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
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reg = <0x24 0x4>;
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};
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shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
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reg = <0x28 0x4>;
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};
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shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
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reg = <0x2c 0x4>;
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};
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shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
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reg = <0x30 0x4>;
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};
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shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
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reg = <0x34 0x4>;
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};
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shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
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reg = <0x38 0x4>;
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};
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shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
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reg = <0x4c 0x4>;
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};
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shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
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reg = <0x50 0x4>;
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};
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shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
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reg = <0x54 0x4>;
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};
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shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
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reg = <0x58 0x4>;
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};
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};
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};
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ethernet-switch {
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compatible = "airoha,an8855-switch";
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reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
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airoha,ext-surge;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "wan";
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phy-mode = "internal";
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phy-handle = <&internal_phy1>;
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&internal_phy2>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&internal_phy3>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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phy-mode = "internal";
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phy-handle = <&internal_phy4>;
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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mdio {
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compatible = "airoha,an8855-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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internal_phy1: phy@1 {
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reg = <1>;
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nvmem-cells = <&shift_sel_port0_tx_a>,
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<&shift_sel_port0_tx_b>,
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<&shift_sel_port0_tx_c>,
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<&shift_sel_port0_tx_d>;
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nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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};
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internal_phy2: phy@2 {
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reg = <2>;
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nvmem-cells = <&shift_sel_port1_tx_a>,
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<&shift_sel_port1_tx_b>,
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<&shift_sel_port1_tx_c>,
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<&shift_sel_port1_tx_d>;
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nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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};
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internal_phy3: phy@3 {
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reg = <3>;
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nvmem-cells = <&shift_sel_port2_tx_a>,
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<&shift_sel_port2_tx_b>,
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<&shift_sel_port2_tx_c>,
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<&shift_sel_port2_tx_d>;
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nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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};
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internal_phy4: phy@4 {
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reg = <4>;
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nvmem-cells = <&shift_sel_port3_tx_a>,
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<&shift_sel_port3_tx_b>,
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<&shift_sel_port3_tx_c>,
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<&shift_sel_port3_tx_d>;
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nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_flash_pins>;
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status = "okay";
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spi_nand@0 {
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compatible = "spi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <52000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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mediatek,nmbm;
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mediatek,bmt-max-ratio = <1>;
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mediatek,bmt-max-reserved-blocks = <64>;
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partitions: partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "BL2";
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reg = <0x0000000 0x0100000>;
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read-only;
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};
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partition@100000 {
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label = "Nvram";
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reg = <0x0100000 0x0040000>;
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read-only;
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};
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partition@140000 {
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label = "Bdata";
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reg = <0x0140000 0x0040000>;
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read-only;
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};
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factory: partition@180000 {
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label = "Factory";
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reg = <0x0180000 0x0200000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_4: macaddr@4 {
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compatible = "mac-base";
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reg = <0x4 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@380000 {
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label = "FIP";
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reg = <0x0380000 0x0200000>;
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read-only;
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};
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partition@580000 {
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label = "crash";
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reg = <0x0580000 0x0040000>;
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read-only;
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};
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partition@5c0000 {
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label = "crash_log";
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reg = <0x05c0000 0x0040000>;
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read-only;
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};
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partition@600000 {
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label = "ubi";
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reg = <0x0600000 0x7000000>;
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};
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partition@7600000 {
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label = "KF";
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reg = <0x7600000 0x0040000>;
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read-only;
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};
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};
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};
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "wan";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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&pio {
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spi0_flash_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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conf-pd {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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status = "okay";
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mediatek,mtd-eeprom = <&factory 0x0>;
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};
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