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99 lines
3.5 KiB
Diff
99 lines
3.5 KiB
Diff
From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Mon, 19 Feb 2024 15:36:33 +0000
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Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
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The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
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in the SRAM control block. If bit 16 is set (the reset value), the
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temperature readings of the THS are way off, leading to reports about
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200C, at normal ambient temperatures. Clearing this bits brings the
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reported values down to the expected values.
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The BSP code clears this bit in firmware (U-Boot), and has an explicit
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comment about this, but offers no real explanation.
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Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
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visibility: all tested bit settings still allow full read and write
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access by the CPU to the whole of SRAM C. Only bit 24 of the register at
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offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
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the THS switch functionality as an SRAM region would not reflect reality.
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Since we should not rely on firmware settings, allow other code (the THS
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driver) to access this register, by exporting it through the already
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existing regmap. This mimics what we already do for the LDO control and
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the EMAC register.
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To avoid concurrent accesses to the same register at the same time, by
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the SRAM switch code and the regmap code, use the same lock to protect
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the access. The regmap subsystem allows to use an existing lock, so we
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just need to hook in there.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com
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---
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drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
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1 file changed, 22 insertions(+)
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--- a/drivers/soc/sunxi/sunxi_sram.c
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+++ b/drivers/soc/sunxi/sunxi_sram.c
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@@ -284,6 +284,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
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struct sunxi_sramc_variant {
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int num_emac_clocks;
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bool has_ldo_ctrl;
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+ bool has_ths_offset;
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};
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static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
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@@ -305,8 +306,10 @@ static const struct sunxi_sramc_variant
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static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
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.num_emac_clocks = 2,
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+ .has_ths_offset = true,
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};
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+#define SUNXI_SRAM_THS_OFFSET_REG 0x0
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#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
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#define SUNXI_SYS_LDO_CTRL_REG 0x150
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@@ -315,6 +318,8 @@ static bool sunxi_sram_regmap_accessible
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{
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const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
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+ if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
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+ return true;
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if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
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reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
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return true;
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@@ -324,6 +329,20 @@ static bool sunxi_sram_regmap_accessible
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return false;
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}
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+static void sunxi_sram_lock(void *_lock)
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+{
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+ spinlock_t *lock = _lock;
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+
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+ spin_lock(lock);
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+}
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+
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+static void sunxi_sram_unlock(void *_lock)
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+{
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+ spinlock_t *lock = _lock;
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+
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+ spin_unlock(lock);
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+}
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+
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static struct regmap_config sunxi_sram_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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@@ -333,6 +352,9 @@ static struct regmap_config sunxi_sram_r
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/* other devices have no business accessing other registers */
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.readable_reg = sunxi_sram_regmap_accessible_reg,
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.writeable_reg = sunxi_sram_regmap_accessible_reg,
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+ .lock = sunxi_sram_lock,
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+ .unlock = sunxi_sram_unlock,
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+ .lock_arg = &sram_lock,
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};
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static int __init sunxi_sram_probe(struct platform_device *pdev)
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