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404209f6c4
kernel: bump to 4.14.193, 4.19.138, 5.4.59 (#5350) 431fb8c mac80211: add AQL improvements 6bdd4c9 mac80211: add missing backports for building with 4.14 kernels 0106820 mac80211: add missing return code checks in AQL improvements e7f7101 mac80211: rework encapsulation offload support [package] base-files: add function for generating random MAC dnsmasq: abort dhcp_check on interface state boot: sync upstream source code ath10k-ct-firmware/mt76/sch_cake: update to latest git HEAD [script] download: add China Mirror Station [target] Sync: arc770, ath79, bcm63xx, kirkwood, lantiq, layerscape, mediatek, mvebu, octeon, oxnas, pistachio, uml Sync most of the target patches. Run-compiled-on: ipq40xx (4.19 & 5.4), ramips
88 lines
2.7 KiB
Diff
88 lines
2.7 KiB
Diff
From 30521ccfb4597f91b9e5c7967acef9c7c85e58a8 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Wed, 12 Aug 2020 22:50:26 +0200
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Subject: [PATCH v2 447/447] mtd: spinand: gigadevice: Add support for
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GD5F4GQ4xC
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This adds support for the following 4GiB chips:
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GD5F4GQ4RCYIG 1.8V
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GD5F4GQ4UCYIG 3.3V
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The datasheet can be found here:
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https://www.novitronic.ch/sixcms/media.php/2/DS-00173-GD5F4GQ4xCxIG-Rev1.574695.pdf
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The GD5F4GQ4UCYIGT (3.3V) version is used on the Imagination
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Technologies Creator Ci40 (Marduk), the 1.8V version was not tested.
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This device only works in single SPI mode and not in dual or quad mode
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for me on this board.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/mtd/nand/spi/gigadevice.c | 49 +++++++++++++++++++++++++++++++
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1 file changed, 49 insertions(+)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -132,6 +132,35 @@ static const struct mtd_ooblayout_ops gd
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.free = gd5fxgq4_variant2_ooblayout_free,
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};
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+static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *oobregion)
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+{
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+ if (section)
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+ return -ERANGE;
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+
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+ oobregion->offset = 128;
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+ oobregion->length = 128;
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+
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+ return 0;
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+}
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+
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+static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *oobregion)
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+{
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+ if (section)
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+ return -ERANGE;
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+
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+ oobregion->offset = 1;
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+ oobregion->length = 127;
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+
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+ return 0;
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+}
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+
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+static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = {
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+ .ecc = gd5fxgq4xc_ooblayout_256_ecc,
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+ .free = gd5fxgq4xc_ooblayout_256_free,
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+};
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+
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static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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@@ -222,6 +251,24 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GQ4RC", 0xa468,
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+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
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+ gd5fxgq4ufxxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GQ4UC", 0xb468,
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+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
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+ gd5fxgq4ufxxg_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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