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https://github.com/coolsnowwolf/lede.git
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228 lines
7.1 KiB
Diff
228 lines
7.1 KiB
Diff
From 61c0ac431798861b0696ccc549138b2eec8a4766 Mon Sep 17 00:00:00 2001
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From: David Wu <david.wu@rock-chips.com>
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Date: Sat, 24 Sep 2022 18:29:52 +0800
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Subject: [PATCH] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3528
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Add constants and callback functions for the dwmac on RK3528 Soc.
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As can be seen, the base structure is the same. In addition, there
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is an internal phy inside with Gmac0.
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Signed-off-by: David Wu <david.wu@rock-chips.com>
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Change-Id: I8a69a1239ed3ae91bfe44c96287210da758f9cf9
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---
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.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 179 +++++++++++++++++-
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1 file changed, 173 insertions(+), 6 deletions(-)
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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@@ -1140,6 +1140,201 @@ static const struct rk_gmac_ops rk3399_o
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.set_rmii_speed = rk3399_set_rmii_speed,
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};
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+#define RK3528_VO_GRF_GMAC_CON 0X60018
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+#define RK3528_VPU_GRF_GMAC_CON5 0X40018
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+#define RK3528_VPU_GRF_GMAC_CON6 0X4001c
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+
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+#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
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+#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
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+#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
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+#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
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+
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+#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
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+#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
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+
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+#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
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+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
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+#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
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+
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+#define RK3528_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(12)
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+#define RK3528_GMAC1_CLK_SELET_IO GRF_BIT(12)
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+
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+#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
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+#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
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+#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
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+#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
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+
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+#define RK3528_GMAC1_CLK_RGMII_DIV1 \
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+ (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
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+#define RK3528_GMAC1_CLK_RGMII_DIV5 \
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+ (GRF_BIT(11) | GRF_BIT(10))
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+#define RK3528_GMAC1_CLK_RGMII_DIV50 \
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+ (GRF_BIT(11) | GRF_CLR_BIT(10))
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+
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+#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
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+#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
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+#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
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+#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
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+
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+#define RK3528_VO_GRF_MACPHY_CON0 0X6001c
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+#define RK3528_VO_GRF_MACPHY_CON1 0X60020
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+
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+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
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+ int tx_delay, int rx_delay)
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+{
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+ struct device *dev = &bsp_priv->pdev->dev;
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+
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+ if (IS_ERR(bsp_priv->grf)) {
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+ dev_err(dev, "Missing rockchip,grf property\n");
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+ return;
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+ }
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+
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ RK3528_GMAC1_PHY_INTF_SEL_RGMII);
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+
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
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+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
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+
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
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+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
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+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
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+}
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+
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+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
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+{
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+ struct device *dev = &bsp_priv->pdev->dev;
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+ unsigned int id = bsp_priv->id;
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+
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+ if (IS_ERR(bsp_priv->grf)) {
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+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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+ return;
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+ }
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+
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+ if (id == 1)
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
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+ RK3528_GMAC1_PHY_INTF_SEL_RMII);
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+ else
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+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
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+ RK3528_GMAC0_PHY_INTF_SEL_RMII);
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+}
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+
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+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
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+{
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+ struct device *dev = &bsp_priv->pdev->dev;
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+ unsigned int val = 0;
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+
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+ switch (speed) {
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+ case 10:
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+ val = RK3528_GMAC1_CLK_RGMII_DIV50;
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+ break;
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+ case 100:
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+ val = RK3528_GMAC1_CLK_RGMII_DIV5;
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+ break;
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+ case 1000:
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+ val = RK3528_GMAC1_CLK_RGMII_DIV1;
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+ break;
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+ default:
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+ goto err;
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+ }
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+
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
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+ return;
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+err:
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+ dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed);
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+}
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+
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+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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+{
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+ struct device *dev = &bsp_priv->pdev->dev;
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+ unsigned int val, offset, id = bsp_priv->id;
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+
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+ switch (speed) {
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+ case 10:
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+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 :
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+ RK3528_GMAC0_CLK_RMII_DIV20;
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+ break;
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+ case 100:
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+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 :
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+ RK3528_GMAC0_CLK_RMII_DIV2;
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+ break;
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+ default:
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+ goto err;
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+ }
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+
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+ offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON;
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+ regmap_write(bsp_priv->grf, offset, val);
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+
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+ return;
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+err:
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+ dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed);
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+}
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+
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+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
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+ bool input, bool enable)
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+{
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+ unsigned int value, id = bsp_priv->id;
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+
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+ if (id == 1) {
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+ value = input ? RK3528_GMAC1_CLK_SELET_IO :
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+ RK3528_GMAC1_CLK_SELET_CRU;
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+ value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
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+ RK3528_GMAC1_CLK_RMII_GATE;
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+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value);
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+ } else {
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+ value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
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+ RK3528_GMAC0_CLK_RMII_GATE;
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+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value);
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+ }
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+}
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+
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+/* Integrated FEPHY */
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+#define RK_FEPHY_SHUTDOWN GRF_BIT(1)
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+#define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
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+#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
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+#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
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+#define RK_FEPHY_PHY_ID GRF_BIT(11)
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+
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+#define RK_FEPHY_BGS HIWORD_UPDATE(0x0, 0xf, 0)
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+
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+static void rk3528_integrated_sphy_power(struct rk_priv_data *priv)
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+{
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+ struct device *dev = &priv->pdev->dev;
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+
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+ if (IS_ERR(priv->grf) || !priv->phy_reset) {
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+ dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
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+ __func__);
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+ return;
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+ }
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+
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+ unsigned int bgs = RK_FEPHY_BGS;
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+
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+ reset_control_assert(priv->phy_reset);
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+ udelay(20);
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+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
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+ RK_FEPHY_POWERUP |
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+ RK_FEPHY_INTERNAL_RMII_SEL |
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+ RK_FEPHY_24M_CLK_SEL |
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+ RK_FEPHY_PHY_ID);
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+
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+ /*if (priv->otp_data > 0)
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+ bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);*/
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+
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+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON1, bgs);
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+ usleep_range(10 * 1000, 12 * 1000);
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+ reset_control_deassert(priv->phy_reset);
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+ usleep_range(50 * 1000, 60 * 1000);
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+}
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+
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+static const struct rk_gmac_ops rk3528_ops = {
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+ .set_to_rgmii = rk3528_set_to_rgmii,
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+ .set_to_rmii = rk3528_set_to_rmii,
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+ .set_rgmii_speed = rk3528_set_rgmii_speed,
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+ .set_rmii_speed = rk3528_set_rmii_speed,
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+ .set_clock_selection = rk3528_set_clock_selection,
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+ .integrated_phy_powerup = rk3528_integrated_sphy_power,
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+};
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+
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#define RK3568_GRF_GMAC0_CON0 0x0380
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#define RK3568_GRF_GMAC0_CON1 0x0384
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#define RK3568_GRF_GMAC1_CON0 0x0388
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@@ -2255,6 +2450,7 @@ static const struct of_device_id rk_gmac
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{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
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{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
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{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
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+ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
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{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
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{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
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{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
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