mirror of
https://github.com/coolsnowwolf/lede.git
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178 lines
6.3 KiB
Diff
178 lines
6.3 KiB
Diff
From 16f512f1e10375dc48aa6c26cedeb7079aba01de Mon Sep 17 00:00:00 2001
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From: Joseph Chen <chenjh@rock-chips.com>
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Date: Sat, 13 Aug 2022 01:15:20 +0000
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Subject: [PATCH] clk: rockchip: Add clock controller for the RK3528
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Add the clock tree definition for the new RK3528 SoC.
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gmac1 clocks are all controlled by GRF, but CRU helps to abstract
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these two clocks for gmac1 since the clock source is from CRU.
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The io-in clocks are module phy output clock, gating child
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clocks by disabling phy output but not CRU gate.
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Add gmac0 clocks.
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They are all orphans if clk_gmac0_io_i is not registered by
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GMAC driver. But it's fine that GMAC driver only get it but
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not to set/get rate.
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Add CLK_SET_RATE_PARENT for mclk_sai_i2s0/1.
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Allowed to change parent rate.
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Add CLK_SET_RATE_NO_REPARENT for dclk_vop0.
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dclk_vop0 is often used for HDMI, it prefers parent clock from
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clk_hdmiphy_pixel_io for better clock quality and any rate.
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It assigns clk_hdmiphy_pixel_io as parent in dts and hope not to
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change parent any more.
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Add CLK_SET_RATE_PARENT for aclk_gpu.
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Allow aclk_gpu and aclk_gpu_mali to change parent rate.
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Add CLK_SET_RATE_PARENT for aclk_rkvdec_pvtmux_root.
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Allow aclk_rkvdec_pvtmux_root and aclk_rkvdec to change parent rate.
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set aclk_m_core = core_clk/2.
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aclk_m_core signoff is 550M, but we set div=2 for better
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performance.
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Add CLK_IS_CRITICAL for clk_32k.
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Mainly for pvtpll during reboot stage.
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Add CLK_IS_CRITICAL for all IOC clocks.
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IOC doesn't share clock with GRF. The iomux can't be changed if they
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are disabled.
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Disable aclk_{vpu,vpu_l,vo}_root rate change
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They are all shared by multiple modules, disable rate change
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by modules.
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Don't register clk_uart_jtag
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It's for force jtag uart delay counter. It must be open
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for box product without tf card but with uart0.
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Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224
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---
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drivers/clk/rockchip/Kconfig | 7 +
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drivers/clk/rockchip/Makefile | 1 +
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drivers/clk/rockchip/clk-rk3528.c | 1187 +++++++++++++++++++++++++++++
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drivers/clk/rockchip/clk.h | 28 +
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4 files changed, 1223 insertions(+)
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create mode 100644 drivers/clk/rockchip/clk-rk3528.c
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--- a/drivers/clk/rockchip/Kconfig
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+++ b/drivers/clk/rockchip/Kconfig
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@@ -93,6 +93,13 @@ config CLK_RK3399
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help
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Build the driver for RK3399 Clock Driver.
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+config CLK_RK3528
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+ bool "Rockchip RK3528 clock controller support"
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+ depends on ARM64 || COMPILE_TEST
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+ default y
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+ help
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+ Build the driver for RK3528 Clock Driver.
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+
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config CLK_RK3568
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bool "Rockchip RK3568 clock controller support"
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depends on ARM64 || COMPILE_TEST
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--- a/drivers/clk/rockchip/Makefile
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+++ b/drivers/clk/rockchip/Makefile
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@@ -27,4 +27,5 @@ obj-$(CONFIG_CLK_RK3308) += clk-r
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obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
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obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
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obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
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+obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o
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obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
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--- a/drivers/clk/rockchip/clk.c
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+++ b/drivers/clk/rockchip/clk.c
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@@ -515,6 +515,14 @@ void rockchip_clk_register_branches(stru
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ctx->reg_base + list->gate_offset,
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list->gate_shift, list->gate_flags, &ctx->lock);
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break;
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+ case branch_gate_no_set_rate:
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+ flags &= ~CLK_SET_RATE_PARENT;
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+
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+ clk = clk_register_gate(NULL, list->name,
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+ list->parent_names[0], flags,
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+ ctx->reg_base + list->gate_offset,
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+ list->gate_shift, list->gate_flags, &ctx->lock);
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+ break;
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case branch_composite:
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clk = rockchip_clk_register_branch(list->name,
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list->parent_names, list->num_parents,
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--- a/drivers/clk/rockchip/clk.h
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+++ b/drivers/clk/rockchip/clk.h
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@@ -207,6 +207,34 @@ struct clk;
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#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
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#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
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+#define RK3528_PMU_CRU_BASE 0x10000
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+#define RK3528_PCIE_CRU_BASE 0x20000
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+#define RK3528_DDRPHY_CRU_BASE 0x28000
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+#define RK3528_VPU_GRF_BASE 0x40000
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+#define RK3528_VO_GRF_BASE 0x60000
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+#define RK3528_SDMMC_CON0 (RK3528_VO_GRF_BASE + 0x24)
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+#define RK3528_SDMMC_CON1 (RK3528_VO_GRF_BASE + 0x28)
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+#define RK3528_SDIO0_CON0 (RK3528_VPU_GRF_BASE + 0x4)
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+#define RK3528_SDIO0_CON1 (RK3528_VPU_GRF_BASE + 0x8)
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+#define RK3528_SDIO1_CON0 (RK3528_VPU_GRF_BASE + 0xc)
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+#define RK3528_SDIO1_CON1 (RK3528_VPU_GRF_BASE + 0x10)
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+#define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
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+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
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+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
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+#define RK3528_MODE_CON 0x280
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+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
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+#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
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+#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
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+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
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+#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
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+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
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+#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
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+#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
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+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
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+#define RK3528_GLB_CNT_TH 0xc00
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+#define RK3528_GLB_SRST_FST 0xc08
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+#define RK3528_GLB_SRST_SND 0xc0c
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+
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#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
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#define RK3568_MODE_CON0 0xc0
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#define RK3568_MISC_CON0 0xc4
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@@ -345,6 +373,7 @@ struct rockchip_pll_clock {
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};
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#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
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+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
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#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
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_lshift, _pflags, _rtable) \
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@@ -448,6 +477,7 @@ enum rockchip_clk_branch_type {
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branch_muxgrf,
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branch_divider,
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branch_fraction_divider,
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+ branch_gate_no_set_rate,
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branch_gate,
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branch_mmc,
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branch_inverter,
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@@ -768,6 +798,19 @@ struct rockchip_clk_branch {
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.name = cname, \
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.parent_names = (const char *[]){ pname }, \
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.num_parents = 1, \
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+ .flags = f, \
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+ .gate_offset = o, \
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+ .gate_shift = b, \
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+ .gate_flags = gf, \
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+ }
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+
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+#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf) \
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+ { \
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+ .id = _id, \
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+ .branch_type = branch_gate_no_set_rate, \
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+ .name = cname, \
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+ .parent_names = (const char *[]){ pname }, \
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+ .num_parents = 1, \
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.flags = f, \
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.gate_offset = o, \
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.gate_shift = b, \
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