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Backport patch allowing to set the MDIO bus clock frequency. By default the MDIO bus clock runs on 2.5 MHz, allow increasing it up to 25 MHz. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
38 lines
1.2 KiB
Diff
38 lines
1.2 KiB
Diff
From 3fb8841513c4ec3a2e5d366df86230c45f239a57 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Sat, 13 Aug 2022 13:08:22 +0200
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Subject: [PATCH 03/10] net: mt7531: ensure all MACs are powered down before
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reset
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The datasheet [1] explicit describes it as requirement for a reset.
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[1] MT7531 Reference Manual for Development Board rev 1.0, page 735
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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---
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drivers/net/dsa/mt7530.c | 6 +++++-
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1 file changed, 5 insertions(+), 1 deletion(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -2412,7 +2412,7 @@ mt7531_setup(struct dsa_switch *ds)
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struct mt7530_priv *priv = ds->priv;
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struct mt7530_dummy_poll p;
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u32 val, id;
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- int ret;
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+ int ret, i;
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/* Reset whole chip through gpio pin or memory-mapped registers for
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* different type of hardware
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@@ -2444,6 +2444,10 @@ mt7531_setup(struct dsa_switch *ds)
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return -ENODEV;
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}
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+ /* all MACs must be forced link-down before sw reset */
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+ for (i = 0; i < MT7530_NUM_PORTS; i++)
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+ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
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+
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/* Reset the switch through internal reset */
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mt7530_write(priv, MT7530_SYS_CTRL,
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SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
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