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https://github.com/coolsnowwolf/lede.git
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36 lines
1.5 KiB
Diff
36 lines
1.5 KiB
Diff
From ceeec9e4dbd9561b9483b3ad8648e66eba3c8016 Mon Sep 17 00:00:00 2001
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From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Date: Thu, 14 Sep 2023 12:30:00 +0530
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Subject: [PATCH 30/41] arm64: dts: qcom: ipq9574: include the GPLL0 as clock
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provider for mailbox
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While the kernel is booting up, APSS clock / CPU clock will be running
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at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
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APSS PLL will be configured to the rate based on the opp table and the
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source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
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consume the GPLL0, with this inclusion, CPU Freq correctly reports that
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CPU is running at 800MHz rather than 24MHz.
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Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-10-c8ceb1a37680@quicinc.com
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[bjorn: Updated commit message, as requested by Kathiravan]
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -507,8 +507,8 @@
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"qcom,ipq6018-apcs-apps-global";
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reg = <0x0b111000 0x1000>;
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#clock-cells = <1>;
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- clocks = <&a73pll>, <&xo_board_clk>;
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- clock-names = "pll", "xo";
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+ clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
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+ clock-names = "pll", "xo", "gpll0";
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#mbox-cells = <1>;
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};
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